Fujitsu MB90460 Series Hardware Manual page 406

Table 15.4-8 Input Control Lower Register (IPCLR) Bits
Bit name
CPE1, CPE0:
bit7,
Input polarity
bit6
selection bits
SNC2 to
bit5 SNC0:
to Noise filter
bit3 enable bits for
SNI2 to SNI0
bit2 SEE2 to SEE0:
to SNI2 to SNI0
bit0 enable bits
• Input polarity selection bits.
• These bits are used to select the polarity of the input edge for the position detection,
the position detection operates according to the input edge polarity set to these bits.
• These bits are used to select the noise cancellation function when the inputs of the
pins SNI2 to SNI0 are enable.
• The noise cancellation circuit starts the internal n-bit counter when an active level is
inputted (the value of n can be 2, 3, 4, 5, which depends on the setting of S21,S20,
S11,S10 and S01,S00 bits in the Noise Cancellation Register). If the active level is
held until the counter overflows, the circuit accepts input from the SNI2 to SNI0
pins. Therefore, the pulse width of noise that can be cancelled is about 2
cycles.
(Note)
When the noise cancellation circuit is enable, the input becomes invalid in a mode
such as STOP mode in which the internal clock is stopped.
• Pins SNI2 to SNI0 edge detection enable bits.
• When they are set to "1", the edge detection of the pins SNI2 to SNI0 are enable.
• Please set these bits before setting CMPE to "1".
CHAPTER 15 MULTI-PULSE GENERATOR
Function
n
machine
387