Fujitsu MB90460 Series Hardware Manual page 496

Table 17.4-1 Serial Control Register (SCR0/SCR1)
Bit name
PEN:
bit15
Parity enable bit
P:
bit14
Parity selection bit
SBL:
bit13 Stop bit length
selection bit
CL:
bit12 Data length selection
bit
A/D:
bit11 Address/data selection
bit
REC:
bit10 Reception error flag
clear bit
RXE:
bit9
Reception enable bit
TXE:
bit8 Transmission enable
bit
• This bit selects whether to add a parity bit during transmission in serial data input-
output mode or to detect it during reception.
(Note)
No parity can be used in operation modes 1 and 2. Therefore, fix this bit to "0".
• When parity is provided (PEN = 1), this bit selects an even or odd parity.
• This bit selects the length of the stop bits or the frame end mark of send data in
asynchronous transfer mode.
(Note)
During reception, only the first bit of the stop bits is detected.
• This bit specifies the length of send and receive data.
(Note)
Seven bits can be selected in operation mode 0 (asynchronous) only. Be sure to
select eight bits (CL = 1) in operation mode 1
operation mode 2 (synchronous).
• Specify the data format of a frame to be sent or received in multiprocessor mode
(mode 1).
• Select usual data when this bit is "0", and select address data when the bit is "1".
• This bit clears the FRE, ORE and PE flags of the status register (SSR).
• Write "0" to this bit to clear the FRE, ORE and PE flag. Writing "1" to this bit has
no effect on the others.
(Note)
If UART is active and a reception interrupt is enabled, clear the REC bit only when
the FRE, DRE or PE flag indicates 1.
• This bit controls UART reception.
• When this bit is "0", reception is disabled. When it is "1", reception is enabled.
(Note)
If this bit is cleared during reception, reception can only be disabled until the
reception of current frame is completed and the reception data is stored in the
reception data is stored in the input data register SIDR0/SIDR1.
• This bit controls UART transmission.
• When this bit is "0", transmission is disabled. When the bit is "1", transmission is
enabled.
(Note)
If this bit is cleared during transmission, transmission can only be disabled until all
data in the output data register SOR0/SOR1 has been transmitted.
CHAPTER 17 UART
Function
(multiprocessor mode) and
477