Fujitsu MB90460 Series Hardware Manual page 405

CHAPTER 15 MULTI-PULSE GENERATOR
■ Input Control Lower Register (IPCLR)
Address bit 7
00008C CPE1 CPE0
H
R/W R/W
X : Indeterminate
R/W : Readable and writable
: Initial value
— : Not used
386
Figure 15.4-9 Input Control Lower Register (IPCLR)
6 5 4 3
SNC2 SNC1 SNC0
R/W R/W R/W
2 1 0 Initial value
SEE2 SEE1 SEE0 00000000
R/W R/W R/W
SEE0
0 Disable SNI0 edge detection. (Initial value)
1
SEE1
0 Disable SNI1 edge detection. (Initial value)
1
SEE2
0 Disable SNI2 edge detection. (Initial value)
1
SNC0 Noise filter enable bit for SNI0
SNI0 input do not go through the noise
0
cancellation circuit.
SNI0 input goes through the noise cancellation
1
circuit.
SNC1 Noise filter enable bit for SNI1
SNI1 input do not go through the noise
0
cancellation circuit.
SNI1 input goes through the noise cancellation
1
circuit.
SNC2 Noise filter enable bit for SNI2
SNI2 input do not go through the noise
0
cancellation circuit.
SNI2 input goes through the noise cancellation
1
circuit.
CPE1 CPE0
0 0
0 1
1 0
1 1
B
SNI0 enable bit
Enable SNI0 edge detection.
SNI1 enable bit
Enable SNI1 edge detection.
SNI2 enable bit
Enable SNI2 edge detection.
Edge selection bits
No edge detection. (stopped state)
(Initial value)
Rising edge detection. ↑
Falling edge detection. ↓
Both edges detection. ↑ & ↓