Direct Page Register (Dpr) - Fujitsu MB90460 Series Hardware Manual

3.7.8

Direct Page Register (DPR)

The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to
addr15) of the operand address when a short direct addressing instruction is executed.
■ Direct Page Register (DPR)
As shown in Figure 3.7-14, the DPR specifies bits 8 to 15 (addr8 to addr15) of the operand address when a
short direct addressing instruction is executed. The DPR is 8-bits long. The DPR is initialized to 01
reset. The DPR can be read and written using an instruction.
Figure 3.7-14 Physical Address Generation by the Direct Page Register (DPR)
24-bit physical address
Figure 3.7-15 shows an example of direct page register (DPR) setting and data access.
Figure 3.7-15 Example of Direct Page Register (DPR) Setting and Data Access
MOV S:56H, #5AH
DTB register
αααααααα
MSB
ααααααααββββββββγγγγγγγγ
DTB register
12
H
DPR register
34
H
DDR register
ββββββββ
Instruction execution results
123458
123456
123454
CHAPTER 3 CPU
Direct address in instruction
γγγγγγγγ
LSB
Memory space
Upper
Lower
8 bits
8 bits
H
5A
H
H
H
MSB
by a
H
LSB
53