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■ Extended Intelligent I/O Service (EI
The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer and I/O
register address pointer, transfer data format (byte or word), and transfer direction. Figure 7.6-5 shows the
configuration of the ISCS.
bit
7
R/W:
Read-write
X:
Undefined
*1
Only the lower 16 bits of the buffer address pointer change. The buffer address pointer
can only be incremented.
*2
The address pointer can only be incremented.
■ Buffer Address Pointer (BAP)
The BAP is a 24-bit register that retains the address used by EI
independent BAP exists for each EI
address in the 16-megabyte space and the I/O. If the BF bit (BAP update/fixed selection bit in the EI
status register) in the EI
BAPL) of the BAP change; the upper 8 bits (BAPH) do not change. Figure 7.6-6 shows the configuration
of the BAP.
Figure 7.6-5 Configuration of EI
6
5
4
3
2
0 must be written to these bits.
2
OS status register (ISCS) is set to "update yes", only the lower 16 bits (BAPM,
2
OS) Status Register (ISCS)
2
OS Status Register (ISCS)
1
0
Initial value
EI
2
OS termination control bit
Not terminated by a request from the peripheral function.
Terminated by a request from the peripheral function
Data transfer direction specification bit
I/O register address pointer → buffer address pointer.
Buffer address pointer → I/O register address pointer
BAP update/fixed selection bit
After data transfer, the buffer address pointer is updated. (*1)
After data transfer, the buffer address pointer is not updated.
Transfer data length specification bit
Byte
Word
IOA update/fixed selection bit
After data transfer, the I/O register address pointer is updated. (*2)
After data transfer, the buffer address pointer is not updated.
Reserved bits
2
OS channel, each EI
CHAPTER 7 INTERRUPT
2
OS for the next transfer. Since one
2
OS channel can transfer data between any
2
OS
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