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●
Transmission interrupt
When transmission data is transferred from the output data register (SODR0/SODR1) to the transfer shift
register, the TDRE bit of the status register (SSR0/SSR1) is set to "1". When the transmission interrupts
have been enabled (SSR0/SSR1: TIE = 1), a transmission interrupt request is output to the interrupt
controller.
■ UART Interrupts and EI
Table 17.5-2 UART Interrupts and EI
Interrupt cause
UART1 reception
interrupt
UART1 transmission
interrupt
UART0 reception
interrupt
UART0 transmission
interrupt
: Provided with a function that detects a UART reception error and stops EI
∆ : Usable when interrupt causes that share the ICR13 and ICR14 or the interrupt vectors are not used
2
■ UART EI
OS Functions
UART has a circuit for operating EI
interrupts.
●
For reception
2
EI
OS can be used regardless of the status of other resources.
●
For transmission
UART shares the interrupt registers (ICR13 and ICR14) with the UART reception interrupts. Therefore,
2
EI
OS can be started up only when no UART reception interrupts are used.
2
OS
2
OS
Interrupt control register
Interrupt number
Register name
#37(25
)
ICR13
H
#38(26
)
ICR13
H
#39(27
)
ICR14
H
#40(28
)
ICR14
H
Address
0000BD
FFFF68
H
0000BD
FFFF64
H
0000BE
FFFF60
H
0000BE
FFFF5C
H
2
OS
2
OS, which can be started up for either reception or transmission
CHAPTER 17 UART
Vector table address
Lower
Upper
Bank
FFFF69
FFFF6A
H
H
FFFF65
FFFF66
H
H
FFFF61
FFFF62
H
H
FFFF5D
FFFF5E
H
H
EI²OS
H
∆
H
H
∆
H
487
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