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21.3.1
Program Aaddress Detection Register (PADR0/PADR1)
The program address detection register (PADR0/PADR1) is a 24-bit register and used to
store the address to be compared with internal address bus.
■ Program Address Detection Register 0/1 (PADR0/PADR1)
Program Address Detection Register 0/1
Address : 1FF2
Address : 1FF5
Read/write
Initial value
The value written to this register is compared with a target address. If the value matches the address, and
the corresponding interrupt enable bit of the PACSR register is "1", the corresponding interrupt bit is set to
"1" to request the CPU to generate an INT9 instruction. If the corresponding interrupt enable bit is "0", no
operation is performed.
Table 21.3-1 lists the correspondence between the program address detection register and PACSR.
Table 21.3-1 Correspondence between Program Address Detection Register and PACSR
Program address detection register
Figure 21.3-2 Program Address Detection Register 0/1
Upper byte
/1FF1
/1FF0
PADRH0
H
H
H
PADRH1
/1FF4
/1FF3
H
H
H
(R/W)
(XXXXXXXX
PADR0
PADR1
CHAPTER 21 ROM CORRECTION FUNCTION
Middle byte
PADRM0
PADRM1
(R/W)
)
(XXXXXXXX
)
(XXXXXXXX
B
B
Interrupt enable bit
AD0E
AD1E
Lower byte
PADR0
PADRL0
PADRL1
PADR1
(R/W)
)
B
Interrupt bit
AD0D
AD1D
575
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