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Table 15.4-1 Output Control Upper Register (OPCUR) Bits
Bit name
DTIE:
bit15
DTTI1 control
enable bit
DTIF:
bit14
DTTI1 interrupt
flag bit
NRSL:
bit13
Noise filter
enable bit
bit12
OPS2 to OPS0:
to
Data transfer
bit10
method selection bits
WTIF:
Write timing
bit9
interrupt flag
bit
WTIE:
Write timing
bit8
interrupt enable
bit
• DTTI1 pin input enable bit.
• This bit is used to enable the DTTI1 pin to control the output levels of the OPT5 to
OPT0 pins. The software can set the inactive level for each OPTx pin in PDRx of
PORTx.
• DTTI1 interrupt request flag.
• It is an interrupt request flag of the DTTI1 input, which is set whenever a falling
edge of DTTI1 is detected and the DTTI1 control enable bit is set to "1".
• When this bit is set to "1", the interrupt is generated. This bit is cleared by writing
"0". Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
• This bit is used to select the noise cancellation function when DTTI1 pin input is
enabled.
• The noise cancellation circuit starts the internal n-bit counter when an active level is
input (the value of n can be 2, 3, 4, 5, which depends on the setting of D1,D0 bits in
the Noise Cancellation Register). If the active level is held until the counter
overflows, the circuit accepts input from the DTTI1 pin. Therefore, the pulse width
of noise that can be cancelled is about 2
(Note)
When the noise cancellation circuit is enable, the input becomes invalid in a mode
such as STOP mode in which the internal clock is stopped.
• OPTx pin output timing control selection bits.
• These bits are used to select the OPDR register write timing control operation mode.
Data is transferred from the Output Data Buffer Register to the Output Data Register
at the write timing controlled by the selected operation mode.
• Write timing interrupt request flag.
• It is an interrupt request flag of the output timing switch, which is set by the write
signal. Data in the OPDBRx register which specified by the BNKF, RDA2 to RDA0
bits in Output Data Register (OPDR) is transferred to the OPDR at the rising edge of
the write signal and the WTIF bit is set to "1".
• When this bit is set to "1", the interrupt is generated if the write timing interrupt
enable bit (WTIE) is also set to "1". This bit is cleared by writing "0". Writing "1"
has no effect.
• In read-modify-write operation, "1" is always read.
• Write timing interrupt enable bit.
• When this bit is set to "1", the interrupt is generated if write timing interrupt request
flag (WTIF) is also set to "1".
CHAPTER 15 MULTI-PULSE GENERATOR
Function
n
machine cycles.
373
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