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CHAPTER 9 I/O PORT
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Port operation after a reset
• When the CPU is reset, the DDR2 register is initialized to "0". As a result, the output buffer is turned
off (I/O mode changes to input), and the pins are placed in a high impedance state.
• The PDR2 register is not initialized when the CPU is reset. To use the port in output mode, therefore,
output mode must be specified in the DDR2 register after the output data is set in the PDR2 register.
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Port operation in stop or time-base timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register (LPMCR) is
already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a high-
impedance state. This is because the output buffer is turned off forcibly regardless of the value in the
DDR2 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit.
Table 9.5-4 lists the states of the port 2 pins.
Table 9.5-4 States of Port 2 Pins
Pin
Normal operation
P20/TIN1 to
General-purpose I/O port General-purpose I/O port General-purpose I/O port
P27/IN3
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
182
Stop mode or time-base timer
Sleep mode
mode (SPL = 0)
Input shut down/output in Hi-Z
Stop mode or time-base
timer mode (SPL = 1)
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