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Software reset
A software reset is an internal reset of three machine cycles (3/φ) generated by writing "0" to the RST bit of
the low power consumption mode control register (LPMCR). The oscillation stabilization wait interval is
not required for software resets.
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Watchdog timer reset
A watchdog timer reset is generated by a watchdog timer overflow that occurs when a "0" is not written to
the WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is
activated. The oscillation stabilization wait interval can be set by the clock selection register (CKSCR).
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Power-on reset
A power-on reset is generated when the power is turned on. The oscillation stabilization wait interval is
18
fixed at 2
oscillation clock cycles (2
elapsed, the reset is executed.
See also
• Definition of clocks
HCLK:
Oscillation clock frequency
MCLK:
Main clock frequency
φ:
Machine clock (CPU operating clock) frequency
1/φ:
Machine cycle (CPU operating clock cycle)
See "5.1 Clock", for details.
18
/HCLK). After the oscillation stabilization wait interval has
CHAPTER 4 RESET
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