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CHAPTER 7 INTERRUPT
Note:
When the extended intelligent I/O service (EI
■ Operation of the Extended Intelligent I/O Service (EI
Figure 7.6-1 shows EI
Figure 7.6-1 Extended Intelligent I/O Service (EI
2
F
MC-16LX
CPU
2
ISD:
EI
OS descriptor
IOA:
I/O address pointer
BAP:
Buffer address pointer
2
ICS:
EI
OS channel selection bit in ICR
DCT:
Data counter
(1) I/O requests transfer.
(2) The interrupt controller selects the descriptor.
(3) The transfer source and transfer destination are read from the descriptor.
(4) Transfer is performed between I/O and memory.
(5) The interrupt cause is automatically cleared.
140
2
OS operation.
Memory space
by IOA
I/O register
(3)
ISD
(3)
by BAP
(4)
Buffer
2
OS) is operating, execution of the CPU program stops.
2
OS)
2
OS) Operation
I/O register
••• ••• ••• ••• •••
Interrupt request (1)
by ICS
(2)
Interrupt control register (ICR)
Interrupt controller
by
DCT
Peripheral
function (I/O)
(5)
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