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M
1
6
C
2 /
9
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15.1.8 Delayed Trigger Mode 1
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the AD
conversion is started. After completing the AN
until the second AD
the single sweep conversion of the pins after the AN
trigger mode 1 specifications. Figure 15.24 shows the operation example of delayed trigger mode 1.
Figure 15.25 and 15.26 show each flag operation in the ADSTAT0 register that corresponds to the
operation example. Figure 15.27 shows registers ADCON0 to ADCON2 in delayed trigger mode 1.
Figure 15.28 shows the ADTRGCON register in delayed trigger mode 1. Table 15.13 shows the trigger
select bit setting in delayed trigger mode 1.
Table 15.12 Delayed Trigger Mode 1 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation Timing
Analog Input Pin
Readout of A/D Conversion Result
NOTES:
1. Do not generate the next AD
complete A/D conversion. When an AD
is ignored. The falling edge of AD
considered to be the next AN0 pin conversion start condition.
___________
2. The AD
pin falling edge is detected synchronized with the operation clock fAD. Therefore, when the AD
TRG
falling edge is generated in shorter periods than fAD, the second AD
not generate the AD
3. Do not write 1 (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write 1,unexpected
interrupts may be generated.
4. AN0
to AN0
, AN 2
0
7
pins need to belong to the same group.
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
___________
TRG
___________
pin falling edge is generated. When the second AD
TRG
Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0
in the ADCON2 register select pins. Analog voltages applied to the selected
pins are converted one-by-one to a digital code. At this time, the
falling edge starts AN
starts conversion of the pins after AN
AN
pin conversion start condition
0
___________
The AD
pin input changes state from "H" to "L" (falling edge)
TRG
AN
pin conversion start condition
1
___________
The AD
pin input changes state from "H" to "L" (falling edge)
TRG
•When the second AD
the AN
pin, input voltage of AN
0
falling edge. The conversion of AN
conversion is completed.
___________
•When the AD
conversion of pins after the AN
•A/D conversion completed
•Set the ADST bit to 0 (A/D conversion halted)
Single sweep conversion completed
Select from AN
and AN
to AN
0
Readout one of
___________
pin falling edge after the AN1 pin conversion is started until all selected pins
TRG
___________
TRG
___________
pin, which was input after all selected pins complete A/D conversion, is
TRG
___________
pin falling edge in shorter periods than fAD.
TRG
to AN2
, and AN3
to AN3
0
7
0
page 247
f o
4
5
8
pin (falling edge) changes state from "H" to "L", a single sweep
pin conversion, the AN
0
pin is restarted. Table 15.12 shows the delayed
1
Specification
pin conversion and the second
0
pin
1
(2)
___________
pin falling edge is generated during A/D conversion of
TRG
pin is sampled or after at the time of AD
1
and the rest of the sweep starts when AN
1
pin falling edge is generated again during single sweep
TRG
pin, the conversion is not affected
1
to AN
(2 pins), AN
0
1
0
(4)
(8 pins)
7
registers
AN0 to AN7 that corresponds to the selected pins
pin falling edge is generated again during A/D conversion, its trigger
___________
can be used in the same way as AN
2
pin is not sampled and converted
1
falling edge is generated,
TRG
___________
AD
___________
AD
pin falling edge
TRG
(1)
(3)
to AN
(4 pins), AN
to AN
3
0
pin falling edge may not be detected. Do
TRG
to AN
0
7
15. A/D Converter
pin
TRG
___________
TRG
0
(6 pins)
5
___________
pin
TRG
. However, all input
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