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17.10.1 Reception
Figure 17.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit
into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first
message.
CANbus
RecReq bit
InvalData bit
NewData bit
MsgLost bit
CAN0 Successful
Reception Interrupt
RecState bit
RecSucc bit
MBOX bit
j = 0 to 15
Figure 17.25 Timing of Receive Data Frame Sequence
(1) On monitoring a SOF on the CAN bus the RecState bit in the C0STR register becomes 1 (CAN module
is receiver) immediately, given the module has no transmission pending.
(2) After successful reception of the message, the NewData bit in the C0MCTLj register (j = 0 to 15) of the
receiving slot becomes 1 (stored new data in slot). The InvalData bit in the C0MCTLj register
becomes 1 (message is being updated) at the same time and the InvalData bit becomes 0 (message is
valid) again after the complete message was transferred to the slot.
(3) When the interrupt enable bit in the C0ICR register of the receiving slot = 1 (interrupt enabled), the
CAN0 successful reception interrupt request is generated and the MBOX bit in the C0STR register is
changed. It shows the slot number where the message was stored and the RecSucc bit in the
C0STR register is active.
(4) Read the message out of the slot after setting the New Data bit to 0 (the content of the slot is read or
still under processing by the CPU) by program.
(5) If the NewData bit is set to 0 by program or the next CAN message is received successfully before the
receive request for the slot is canceled, the MsgLost bit in the C0MCTLj register is set to 1 (message
has been overwritten). The new received message is transferred to the slot. Generating of an
interrupt request and change of the C0STR register are same as in 3).
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SOF
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SOF
ACK
EOF
IFS
(2)
(2)
(3)
ACK
EOF
(5)
(4)
(5)
(5)
Receive slot No.
17. CAN Module
IFS
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