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M
1
6
C
2 /
9
G
o r
u
p
In receive mode, ACK bit = 1 WIT bit = 0
ACKBIT bit
PIN flag
Internal WAIT flag
2
I
C bus interface
interrupt request signal
The writing signal of
the S00 register
In receive mode, ACK bit = 1 WIT bit = 1
ACKBIT bit
PIN flag
Internal WAIT flag
2
I
C bus interface
interrupt request signal
The writing signal of
the S00 register
The writing signal of the S2
0 register
Figure 16.12 The timing of the interrupt generation at the completion of the data receive
16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC
If the ES0 bit in the S1D0 register is set to 1 (I
output port. When the PED bit is set to 1 and the SCL
set to 1. Then the setting values of bits P2_0 and P2_1 in the port P2 register are output to the I
regardless of he internal SCL/SDA output signals. (SCL/SDA pins are onnected to I
circuit)
The bus data can be read by reading the port pi direction register in input mode, regardless of the setting
values of the PED and PEC bits. Table 16.5 shows the port specification.
Table 16.5 Port specifications
P
n i
N
a
m
e
P
2
0
P
n i
N
a
m
e
P
2
1
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
7 clock
8 clock
S
CL
7 bit
8 bit
S
DA
7 clock
8 clock
S
CL
7 bit
8 bit
S
DA
NOTE:
1. Do not write to the
E
S
9
B
t i
P
E
D
0
1
0
1
E
S
0
B
t i
P
E
C
0
1
0
1
page 273
f o
4
5
8
ACK
clock
ACK bit
1)
2
clock control register except the bit ACK-BIT.
I
C0
2
C bus interface enabled), the SDA
functions as an output port when the PEC bit is
MM
P
2
P
o
t r
i D
e r
t c
0
B
t i
R
e
g
t s i
r e
-
0
1 /
-
1
-
P
2
P
o
t r
i D
e r
t c
1
B
t i
R
e
g
t s i
r e
-
0
1 /
-
1
-
16. MULTI-MASTER I
1 clock
1 bit
ACK
clock
2)
MM
o i
n
F
u
n
t c
P
o
t r
/ I
O
u f
n
t c
o i
n
S
/ I
O
u f
n
t c
o i
n
D
A
S
n i
p
t u
u f
n
t c
o i
, n
p
D
A
o i
n
F
u
n
t c
o i
n
P
o
t r
/ I
O
u f
n
t c
o i
n
S
/ I
O
u f
n
t c
o i
n
C
L
S
n i
p
t u
u f
n
t c
o i
, n
p
C
L
2
C bus INTERFACE
1 bit
functions as an
2
C bus,
2
C bus interface
o i
n
o
t r
o
u
p t
t u
u f
n
t c
o i
n
o
t r
o
u
p t
t u
u f
n
c
o i
n
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