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6
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22.8.2 UART Mode
22.8.2.1 Special Mode 1 (I
When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0
and wait for more than half cycle of the transfer clock before setting each condition generate bit
(STAREQ, RSTAREQ and STPREQ) from 0 to 1.
22.8.2.2 Special Mode 2
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1
(three-phase output forcible cutoff by input on SD pin enabled), the RTS
impedance state.
22.8.2.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to 1 (transmission
complete) and U2ERE bit to 1 (error signal output) after reset. Therefore, when using SIM mode, be
sure to clear the IR bit to 0 (no interrupt request) after setting these bits.
22.8.3 SI/O3, SI/O4
The SOUTi default value which is set to the SOUTi pin by the SMi7 bit approximately 10ns may be output
when changing the SMi3 bit from 0 (I/O port) to 1 (SOUTi output and CLKfunction) while the SMi2 bit in
the SiC (i=3 and 4) to 0 (SOUTi output) and the SMi6 bit is set to 1 (internal clock). And then the SOUTi
pin is held high-impedance.
If the level which is output from the SOUTi pin is a problem when changing the SMi3 bit from 0 to 1, set the
default value of the SOUTi pin by the SMi7 bit.
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page 438
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22. Usage Notes
and CLK
pins go to a high-
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