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M
1
6
C
2 /
9
G
o r
u
p
15. A/D Converter
Note
Ports P0
to P0
4
available in 64-pin package. Do not use port P0
and P9
to P9
5
7
The MCU contains one A/D converter circuit based on 10-bit successive approximation method configured
with a capacitive-coupling amplifier. The analog inputs share the pins with P10
to P0
(AN0
to AN0
7
0
____________
Similarly, AD
input shares the pin with P1
TRG
sponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit to 0 (Vref unconnected), so that no current will flow
from the Vref pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for AN
= 0 to 2). Table 15.1 shows the A/D converter performance. Figure 15.1 shows the A/D converter block
diagram and Figures 15.2 to 15.4 show the A/D converter associated with registers.
Table 15.1 A/D Converter Performance
Item
A/D Conversion Method
Analog Input Voltage
Operating Clock φ
AD
Resolution
Integral Nonlinearity Error When AV
Operating Modes
Analog Input Pins
Conversion Speed Per Pin
NOTES:
1. Not dependent on use of sample and hold function.
2. Set the φAD frequency to 10 MHz or less.
Without sample-and-hold function, set the φAD frequency to 250kH
With the sample and hold function, set the φAD frequency to 1MH
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
(AN0
to AN0
), P1
7
4
7
0
(AN2
to AN2
) as analog input pins in 64-pin package.
5
7
), and P1
to P1
, P9
7
0
3
Successive approximation (capacitive coupling amplifier)
0V to AV
(V
(1)
CC
f
/divided-by-2 or f
(2)
AD
or f
/divided-by-12 or f
AD
8-bit or 10-bit (selectable)
= Vref = 5V
CC
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±3LSB
When AV
= Vref = 3.3V
CC
• With 8-bit resolution: ±2LSB
• With 10-bit resolution: ±5LSB
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat
sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1
8 pins (AN
to AN
0
to AN3
)
(80-pin package)
2
8 pins (AN
to AN
0
(64-pin package)
• Without sample and hold function
8-bit resolution: 49 φ
• With sample and hold function
8-bit resolution: 28 φ
page 222
f o
4
5
8
to P1
(AN2
to AN2
) and P9
3
0
3
to P0
(AN0
4
7
, P9
to P9
(AN2
to AN2
3
5
7
0
. Therefore, when using these inputs, make sure the corre-
5
Performance
)
CC
/divided-by-3 or f
AD
AD
) + 8 pins (AN0
to AN0
7
0
) + 4 pins (AN0
to AN0
7
0
cycles, 10-bit resolution: 59 φ
AD
cycles, 10-bit resolution: 33 φ
AD
Z
to P9
(AN2
to AN2
5
7
5
to AN0
), P1
to P1
(AN2
4
7
0
3
to P10
0
7
), and P9
to P9
7
0
, AN0
, AN2
(i = 0 to 7), and AN3
i
i
i
/divided-by-4 or f
AD
AD
) + 8 pins (AN2
to AN2
7
0
) + 1 pin (AN2
) + 3 pins (AN3
3
4
cycles
AD
cycles
AD
or more.
Z
or more.
15. A/D Converter
) are not
7
to AN2
)
0
3
(AN
to AN
), P0
0
7
0
(AN3
to AN3
).
2
0
2
pins (i
i
/divided-by-6
) + 3 pins (AN3
7
0
to AN3
)
0
2
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