Clk Polarity Selection; Oi Operation Timing - Renesas M16C/29 Series User Manual

M 1 6 C 2 / 9 G o r u p
14.2.1 SI/Oi Operation Timing
Figure 14.37 shows the SI/Oi operation timing
SI/Oi internal clock
CLKi output
Signal written to the
SiTRR register
S i output
OUT
S i input
IN
SiIC register
IR bit
i= 3, 4
NOTES:
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi2 = 0 (S i output), SMi3 = 1 (S
OUT
rising edge of the transfer clock), SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock)
2. When the SMi6 bit is set to 0 (internal clock), the S
3. If the SMi6 bit is set to 0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to
the SiTRR register.
Figure 14.37 SI/Oi Operation Timing

14.2.2 CLK Polarity Selection

The the SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 14.38
shows the polarity of the transfer clock.
(1) When the SMi4 bit in the SiC register is set to 0
CLK
i
S
INi
S
OUTi
(2) When the SMi4 bit in the SiC register is set to 1
CLK
i
S
INi
S
OUTi
i=3 and 4
NOTES:
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock)
2. When the SMi6 bit is set to 1 (internal clock), a high level is output from the CLKi pin if not transferring data.
3 When the SMi6 bit is set to 1 (internal clock), a low level is output from the CLKi pin if not transferring data.
Figure 14.38 Polarity of Transfer Clock
R e . v 1 1 . 2 M r a 3 . , 0 2 0 0 7
R E J 0 9 B 0 1 0 1 0 - 1 1 2
1.5 cycle (max)
(3)
"H"
"L"
"H"
"L"
"H"
"L"
"H"
D
"L"
"H"
"L"
1
0
i output, CLKi function), SMi4 = 0 (transmit data output at the falling edge and receive data input at the
OUT
OUT
D0 D D D
1 2 3
D D D D
0 1 2 3
D D D D
0 1 2 3
D D D D
0 1 2 3
page 220
f o 4 5 8
D D D
0 1 2 3
i pin is placed in the high-impedance state after the transfer is completed.
D D D D
4 5 6 7
D D D D
4 5 6 7
D D D D
4 5 6 7
D D D D
4 5 6 7
D D D
4 5 6
(2)
(3)
14. Serial I/O
(2)
D
7