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M
1
6
C
2 /
9
G
o r
u
p
16.12 START/STOP Condition Detect Operation
Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. Bits SSC4
to SSC0 in the S2D0 register set the START/STOP conditions. The START/STOP condition can be de-
tected only when the input signal of the SCL
time, the set-up time, and the hold time (see Table 16.10). The BB flag in the S10 register is set to 1 when
the START condition is detected and it is set to 0 when the STOP condition is detected. The BB flag set and
reset timing varies between standard clock mode and high-speed clock mode. See Table 16.10.
Figure 16.18 Start condition detection timing diagram
Figure 16.19 Stop condition detection timing diagram
Table 16.10 Start/Stop detection timing table
SCL release time
Setup time
Hold time
BB flag set/reset
time
NOTE:
1. Unit : number of cycle for I
The SSC value is the decimal notation value of bits SSC4 to SSC0. Do not set 0 or odd numbers to the SSC
setting. The values in ( ) are examples when the S2D0 register is set to 18
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
S
CL
S
DA
BB flag
S
CL
Setup time
S
DA
BB flag
Standard clock mode
SSC value + 1 cycle (6.25µs)
SSC value + 1 cycle < 4.0µs (3.25µs)
2
SSC value
cycle < 4.0µs (3.0µs)
2
SSC value - 1 +2 cycles (3.375µs)
2
2
C system clock V
page 281
f o
4
5
8
and SDA
met the following conditions: the SCL release
MM
MM
S
release time
CL
Setup time
Hold time
BB flag
set time
S
release time
CL
Hold time
BB flag
set time
IIC
2
16. MULTI-MASTER I
High-speed clock mode
4 cycles (1.0µs)
2 cycles (0.5µs)
2 cycles (0.5µs)
3.5 cycles (0.875µs)
at V
= 4 MHz.
16
IIC
C bus INTERFACE
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