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22.6.2 Timer B
22.6.2.1 Timer B (Timer Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to 1 (count
starts).
Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regard-
less whether after reset or not.
2. The counter value can be read out at any time by reading the TBi register. However, if this register
is read at the same time the counter is reloaded, the read value is always FFFF
is read after setting a value in it but before the counter starts counting, the read value is the one that
has been set in the register.
22.6.2.2 Timer B (Event Counter Mode)
1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to 1 (count
starts).
Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regard-
less whether after reset or not.
2. The counter value can be read out at any time by reading the TBi register. However, if this register
is read at the same time the counter is reloaded, the read value is always FFFF
is read after setting a value in it but before the counter starts counting, the read value is the one that
has been set in the register.
22.6.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2)
register before setting the TBiS bit in the TABSR or the TBSR register to 1 (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regard-
less whether after reset or not. To clear the MR3 bit to 0 by writing to the TBiMR register while the
TBiS bit is set to 1 (count starts), be sure to write the same value as previously written to bits
TM0D0, TM0D1, MR0, MR1, TCK0, and TCK1 and a 0 to the MR2 bit.
2. The IR bit in TBiIC register (i=0 to 2) goes to 1 (interrupt request), when an effective edge of a
measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be deter-
mined by use of the MR3 bit in TBiMR register within the interrupt routine.
3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
4. To set the MR3 bit to 0 (no overflow), set TBiMR register with setting the TBiS bit to 1 and counting
the next count source after setting the MR3 bit to 1 (overflow).
5. Use the IR bit in TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
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22. Usage Notes
. If the TBi register
16
. If the TBi register
16
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