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M
1
6
C
2 /
9
G
o r
u
p
20.8 Status Register
The status register indicates the operating status of the flash memory and whether or not erase or pro-
gram operation is successfully completed. Bits FMR00, FMR06, and FMR07 in the FMR0 register indi-
cate the status of the status register.
Table 20.6 lists the status register.
In EW mode 0, the status register can be read in the following cases:
(1) Any even address in the user ROM area is read after writing the read status register command
(2) Any even address in the user ROM area is read from when the program or block erase command is
executed until when the read array command is executed.
20.8.1 Sequence Status (SR7 and FMR00 Bits )
The sequence status indicates the flash memory operating status. It is set to 0 (busy) while the auto-
program and auto-erase operation is being executed and 1 (ready) as soon as these operations are
completed. This bit indicates 0 (busy) in erase-suspend mode.
20.8.2 Erase Status (SR5 and FMR07 Bits)
Refer to 20.8.4 Full Status Check.
20.8.3 Program Status (SR4 and FMR06 Bits)
Refer to 20.8.4 Full Status Check.
Table 20.6 Status Register
Bits in the
Bits in the
FMR0
SRD Register
Register
SR7 (D
)
FMR00
7
SR6 (D
)
6
SR5 (D
)
FMR07
5
FMR06
SR4 (D
)
4
SR3 (D
)
3
SR2 (D
)
2
SR1 (D
)
1
SR0 (D
)
0
• D
to D
: Indicates the data bus which is read out when executing the read status register command.
7
0
• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to 0 by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase command are not accepted.
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
Status
Name
Sequence status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
page 351
f o
4
5
8
Contents
0
Busy
-
Completed normally
Completed normally
-
-
-
-
20. Flash Memory Version
1
Ready
-
Terminated by error
Terminated by error
-
-
-
-
Value
After
Reset
1
0
0
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