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M
1
6
C
2 /
9
G
o r
u
p
20.8.4 Full Status Check
If an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating a specific error.
Therefore, execution results can be comfirmed by verifying these status bits (full status check).
Table 20.7 lists errors and FMR0 register state. Figure 20.14 shows a flow chart of the full status check
and handling procedure for each error.
Table 20.7 Errors and FMR0 Register Status
FMR0 register
(SRD register)
status
FMR07
FMR06
(SR5)
(SR4)
1
1
1
0
0
1
Note 1: The flash memory enters read array mode by writing command code xxFF
cycle of these commands. The command code written in the first bus cycle becomes invalid.
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
Error
Command
• An incorrect commands is written
sequence error • A value other than xxD0
cycle of the block erase command
• When the block erase command is executed on an protected block
• When the program command is executed on protected blocks
Erase error
• The block erase command is executed on an unprotected block
but the program operation is not successfully completed
Program error
• The program command is executed on an unprotected block but
the program operation is not successfully completed
page 352
f o
4
5
8
Error occurrence condition
or xxFF
is written in the second bus
16
16
(1)
20. Flash Memory Version
in the second bus
16
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