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M
1
6
C
2 /
9
G
o r
u
p
16.9 START Condition Generation Method
Set the MST bit, TRX bit and BB flags in the S10 register to 1 and set the PIN bit and 4 low-order bits in the
S10 register to 0 simultaneously, to enter START condition standby mode, when the ES0 bit in the S1D0
register is set to 1 (I
is written to the S00 register next, START condition is generated and the bit counter is reset to 000
byte SCL signal is output. The START condition generation timing varies between standard clock mode
and high-speed clock mode. See Figure 16.16 and Table 16.8.
Figure 16.14 Start condition generation flow chart
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
2
C bus interface enabled) and the BB flag is set to 0 (bus free). When the slave address
I n t e r r u p t d i s a b l e
BB=0?
Yes
S10 = E0
16
S00 = Data
Interrupt enable
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f o
4
5
8
16. MULTI-MASTER I
N o
Start condition standby status setting
Start condition trigger generation
*Data = Slave address data
2
C bus INTERFACE
and 1-
2
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