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M
1
6
C
2 /
9
G
o r
u
p
2
16.7 I
C0 Control Register 2 (S4D0 Register)
The S4D0 register controls the error communication detection.
If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid
the situation, the I
stopped in high-level ("H") state for a specific period, and to generate an I
See Figure 16.13.
BB flag
Internal counter start signal
Internal counter stop, reset signal
Internal counter overflow signal
2
I
C-bus interface interrupt
request signal
Figure 16.13 The timing of time-out detection
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
2
C bus interface circuit has a function to detect the time-out when the SCL clock is
1 clock
S
CL
1 bit
S
DA
page 275
f o
4
5
8
16. MULTI-MASTER I
2
2 clock
3 clock
2 bit
3 bit
The time of timeout detection
2
C bus INTERFACE
C bus interface interrupt request.
S
clock stop ("H")
CL
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