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7.6 Power Control
There are three power control modes. In this chapter, all modes other than wait and stop modes are
referred to as normal operation mode.
7.6.1 Normal Operation Mode
Normal operation mode is further classified into seven modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the
CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits
are turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source must be in stable
oscillation. If the new clock source is the main clock, sub clock or PLL clock, allow a sufficient wait time
in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low power dissipation mode to on-chip oscil-
lator mode or on-chip oscillator low power dissipation mode. Nor can operation modes be changed
directly from on-chip oscillator mode or on-chip oscillator low power dissipation mode to low power dissi-
pation mode.
When the CPU clock source is changed from the on-chip oscillator to the main clock, change the opera-
tion mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit
in the CM0 register was set to 1) in the on-chip oscillator mode.
7.6.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, f
count source for timers A and B.
7.6.1.2 PLL Operation Mode
The main clock multiplied by 2 or 4 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is on, f
mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop
mode, first go to high speed mode before changing.
7.6.1.3 Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, f
as the count source for timers A and B.
7.6.1.4 Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit is set to 0 (on-chip oscillator turned off), and the on-chip oscillator
clock is used when the CM21 bit is set to 1 (on-chip oscillator oscillating).
The f
clock can be used as the count source for timers A and B.
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7.6.1.5 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock
provides the CPU clock. The f
eral function clock can use only f
Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes 1 (divided by
8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divided by 8) mode is to be selected when the main clock is operated next.
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can be used as the count source for timers A and B. PLL operation
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clock can be used as the count source for timers A and B. Periph-
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.
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7. Clock Generation Circuit
can be used as the
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can be used
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