Bit0: Time-Out Detection Function Enable Bit (Toe); Bit1: Time-Out Detection Flag (Tof ); Bit2: Time-Out Detection Period Select Bit (Tosel); Bits 3,4,5: I 2 C System Clock Select Bits (Ick2-4) - Renesas M16C/29 Series User Manual

M 1 6 C 2 / 9 G o r u p

16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE)

The TOE bit enables the time-out detection function. When the TOE bit is set to 1, time-out is detected
2
and the I C bus interface interrupt request is generated when the following conditions are met.
1) the BB flag in the S10 register is set to 1 (bus busy)
2) the SCL clock stops for time-out detection period while high-level ("H") signal is maintained (see
Table 16.7)
The internal counter measures the time-out detection time and the TOSEL bit selects between two
modes, long time and short time. When time-out is detected, set the ES0 bit to 0 (I
disabled) and reset the counter.

16.7.2 Bit1: Time-Out Detection Flag (TOF )

The TOF flag indicates the time-out detection. If the internal counter which measures the time-out
period overflows, the TOF flag is set to 1 and the I
same time.

16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL)

The TOSEL bit selects time-out detection period from long time mode and short time mode. When the
TOSEL bit is set to 0, long time mode is selected. When it is set to 1, short time mode is selected,
respectively. The internal counter increments as a 16-bit counter in long time mode, while the counter
increments as a 14-bit counter in short time mode, based on the I
source. Table 16.7 shows examples of time-out detection period.
Table 16.7 Examples of Time-out Detection Period
V (MHz)
IIC
4
2
1
16.7.4 Bits 3,4,5: I
Bits ICK4 to ICK2, and bits ICK1 and ICK0 in the S3D0 register, and the PCLK0 bit in the PCLKR register
select the system clock (V

16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN)

The SCPIN bit monitors the stop condition detection interrupt. The SCPIN bit is set to 1 when the I
interface interrupt is generated by detecting the STOP condition. When this bit is set to 0 by program, it
becomes 0. However, no change occurs even if it is set to 1.
R e . v 1 1 . 2 M r a 3 . , 0 2 0 0 7
R E J 0 9 B 0 1 0 1 0 - 1 1 2
Long time mode
16.4
32.8
65.6
2
C System Clock Select Bits (ICK2-4)
2
) of the I C bus interface circuit. See Table 16.6 for the setting values.
IIC
page 276
f o 4 5 8
16. MULTI-MASTER I
2
C bus interface interrupt request is generated at the
2
C system clock (V
(Unit: ms)
Short time mode
4.1
8.2
16.4
2
C bus INTERFACE
2
C bus interface
) as a counter
IIC
2
C bus