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M
1
6
C
2 /
9
G
o r
u
p
16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM
Bits SDAM/SCLM can monitor the logic value of the SDA and SCL output signals from the I
interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL
output logic value. The SDAM and SCLM bits are read-only. If necessary, set them to 0.
16.6.5 Bits 6,7 : I
The ICK1 bit, ICK0 bit, bits ICK4 to ICK2 in the S4D0 register, and the PCLK0 bit in the PCLKR register
can select the system clock (V
2
The I
C bus system clock V
and 1/8 f
. f
IIC
IIC
2
Table 16.6 I
C system clock select bits
I3CK4[S4D0]
0
0
0
0
0
0
1
( Do not set the combination other than the above)
16.6.6 Address Receive in STOP/WAIT Mode
When WAIT mode is entered after the CM02 bit in the CM0 register is set to 0 (do not stop the peripheral
function clock in wait mode), the I
2
ever, the I
C bus interface circuit is not operated in STOP mode or in low power consumption mode,
2
because the I
C bus system clock V
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
2
C System Clock Select Bits ICK0, ICK1
) of the I
IIC
can be selected among 1/2 f
IIC
can be selected between f
ICK3[S4D0]
ICK2[S4D0]
0
0
0
0
1
1
0
2
C bus interface circuit can receive address data in WAIT mode. How-
IIC
page 274
f o
4
5
8
2
C bus interface circuit.
IIC
and f
by the PCLK0 bit setting.
1
2
ICK1[S3D0]
0
0
0
0
0
1
1
X
0
X
1
X
0
X
is not supplied.
16. MULTI-MASTER I
, 1/2.5 f
, 1/3 f
, 1/4 f
IIC
IIC
2
ICK0[S3D0]
I
0
V
1
V
0
V
X
V
X
V
X
V
X
V
2
C bus INTERFACE
2
C bus
, 1/5 f
, 1/6 f
IIC
IIC
IIC
C system clock
= 1/2 f
IIC
IIC
= 1/4 f
IIC
IIC
= 1/8 f
IIC
IIC
= 1/2.5 f
IIC
IIC
= 1/3 f
IIC
IIC
= 1/5 f
IIC
IIC
= 1/6 f
IIC
IIC
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