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6
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o r
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p
15.1.6 Simultaneous Sample Sweep Mode
In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by-
one to a digital code. The input voltages of AN0 and AN1 are sampled simultaneously using two circuits
of sample and hold circuit. Table 15.8 shows the simultaneous sample sweep mode specifications.
Figure 15.16 shows the operation example in simultaneous sample sweep mode. Figure 15.17 shows
registers ADCON0 to ADCON2 and Figure 15.18 shows ADTRGCON registers in simultaneous sample
sweep mode. Table 15.9 shows the trigger select bit setting in simultaneous sample sweep mode. In
simultaneous sample sweep mode, Timer B0 underflow can be selected as a trigger by combining soft-
___________
ware trigger, AD
underflow or A/D trigger mode of Timer B.
Table 15.8 Simultaneous Sample Sweep Mode Specifications
Item
Function
A/D Conversion Start Condition
A/D Conversion Stop Condition
Interrupt Generation Timing A/D conversion completed
Analog Input Pin
Readout of A/D conversion result Readout one of registers AN0 to AN7 that corresponds to the selected pin
NOTE:
1. AN0
to AN0
, AN 2
0
7
pins need to belong to the same group.
•Example when selecting AN
A/D conversion started
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
Figure 15.16 Operation Example in Simultaneous Sample Sweep Mode
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
trigger, Timer B2 underflow, Timer B2 interrupt generation frequency setting counter
TRG
Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and
ADGSEL0 in the ADCON2 register select pins. Analog voltage applied
to the selected pins is converted one-by-one to a digital code. At this time,
the input voltage of AN
When the TRG bit in the ADCON0 register is 0 (software trigger)
Set the ADST bit in the ADCON0 register to 1 (A/D conversion started)
When the TRG bit in the ADCON0 register is 1 (hardware trigger)
The trigger is selected by bits TRG1 and HPTRG0 (See Table 15.9)
The AD
TRG
bit to 1 (A/D conversion started)
Timer B0, B2 or Timer B2 interrupt generation frequency setting counter
underflow after setting the ADST bit to 1 (A/D conversion started)
A/D conversion completed (If selecting software trigger, the ADST bit is
automatically set to 0 ).
Set the ADST bit to 0 (A/D conversion halted)
Select from AN
or AN
to AN
0
to AN2
, and AN3
to AN3
0
7
0
to AN
0
page 238
f o
4
5
8
Specification
and AN
are sampled simultaneously.
0
1
pin input changes state from "H" to "L" after setting the ADST
to AN
(2 pins), AN
0
1
(1)
(8 pins)
7
can be used in the same way as AN
2
to A/D pins for sweep (SCAN1 to SCAN0 = 01
3
A/D interrupt request generated
to AN
(4 pins), AN
to AN
0
3
0
to AN
0
)
2
A/D pin input voltage
sampling
A/D pin conversion
15. A/D Converter
(6 pins),
5
. However, all input
7
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