I Flag; Ir Bit; Ilvl2 To Ilvl0 Bits And Ipl - Renesas M16C/29 Series User Manual

M 1 6 C 2 / 9 G o r u p

9.3.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (= enabled) enables the
maskable interrupt. Setting the I flag to 0 (= disabled) disables all maskable interrupts.

9.3.2 IR Bit

The IR bit is set to 1 (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to 0 (= interrupt not requested).
The IR bit can be cleared to 0 in a program. Note that do not write 1 to this bit.

9.3.3 ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 9.3 shows the settings of interrupt priority levels and Table 9.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. In no case do they affect
one another.
Table 9.3 Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 bits
000 Level 0 (interrupt disabled)
2
001 Level 1
2
010 Level 2
2
011 Level 3
2
100 Level 4
2
101 Level 5
2
110 Level 6
2
111 Level 7
2
R e . v 1 1 . 2 M r a 3 . , 0 2 0 0 7
R E J 0 9 B 0 1 0 1 0 - 1 1 2
Interrupt priority Priority
level order
Low
High
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Table 9.4 Interrupt Priority Levels
Enabled by IPL
IPL Enabled interrupt priority levels
000 Interrupt levels 1 and above are enabled
2
001 Interrupt levels 2 and above are enabled
2
010 Interrupt levels 3 and above are enabled
2
011 Interrupt levels 4 and above are enabled
2
100 Interrupt levels 5 and above are enabled
2
101 Interrupt levels 6 and above are enabled
2
110 Interrupt levels 7 and above are enabled
2
111 All maskable interrupts are disabled
2
9. Interrupts