Event Counter Mode - Renesas M16C/29 Series User Manual

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12.2.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 12.7). Figure 12.19 shows the TBiMR register in event counter mode.
Table 12.7 Specifications in Event Counter Mode
Item
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing Timer underflow
TBi
pin function
IN
Read from timer
Write to timer
NOTE:
1. Bits TB2S to TB0S are assigned to the bit 7 to bit 5 in the TABSR register.
Timer Bi Mode Register (i=0 to 2)
b7
b6
b5
b4
NOTES:
1. Effective when the TCK1 bit is set to 0 (input from TBiIN pin). If the TCK1 bit is set to 1 (TBj overflow or
underflow), these bits can be set to 0 or 1.
2. The port direction bit for the TBi
Figure 12.19 TBiMR Register in Event Counter Mode
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
• External signals input to TBi
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0)
• Decrement
• When the timer underflows, it reloads the reload register contents and
continues counting
1/(n+1)
(1)
Set TBiS bit
Set TBiS bit to 0 (stop counting)
Count source input
Count value can be read by reading TBi register
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
b3
b2
b1
b0
Symbol
0 1
TB0MR to TB2MR
Bit Symbol
TMOD0
Operation mode select bit
TMOD1
MR0
Count polarity select
bit
MR1
TB0MR register
Set to 0 in timer mode
MR2
TB1MR, TB2MR registers
Nothing is assigned. If necessary, set to 0. When read, the
content is undefined
When write in event counter mode, set to 0. When read in event
MR3
counter mode, its content is undefined
No effect in event counter mode
TCK0
Can be set to 0 or 1
TCK1
Event clock select
pin must be set to 0 (= input mode).
IN
page 120
f o
4
5
8
Specification
pin (i=0 to 2) (effective edge can be selected
IN
n: set value of TBi register
to 1 (start counting)
Address
After Reset
039B
to 039D
00XX0000
16
16
Bit Name
b1 b0
0 1: Event counter mode
b3 b2
0 0: Counts external signal's
(1)
falling edges
0 1: Counts external signal's rising
edges
1 0: Counts external signal's
falling and rising edges
1 1: Do not set
0 : Input from TBi
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0)
0000
to FFFF
16
16
2
RW
Function
RW
RW
RW
RW
RW
RO
RW
pin
(2)
IN
RW
12. Timer B

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