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M
1
6
C
2 /
9
G
o r
u
p
13.1.1 Base Timer Reset Register(G1BTRR)
The G1BTRR register provides the capability to reset the base timer when the base timer count value
matches the value stored in the G1BTRR register. The G1BTRR register is enabled by the RST4 bit
in the G1BCR0 register. This function is identical in operation to the G1PO0 base timer reset that is
enabled by the RST1 bit in the G1BCR0 reigster. If the free-running operation is not selected, the
channel 0 can be used for a waveform generation when the base timer is reset by the G1BTRR
register. Do not enable bits RST1 and RST4 simultaneously.
G1BTRR register
(Base timer reset register)
Base timer interrupt
Base timer overflow request
NOTE:
1. Following conditions are required to generate a base timer overflow request by resetting the base timer.
If the IT bit is set to 0: 07FFF
If the IT bit is set to 1: 07FFF
Figure 13.15 Base Timer Reset operation by Base Timer Reset Register
RST1
Base timer
G1PO0
G1IR0
Figure 13.16 Base Timer Reset operation by G1PO0 register
RST2
Base timer
P8
3
NOTE:
________
1. INT1 Base Timer reset does not generate a Base Timer interrupt. INT1 may generate an interrupt if enabled.
Figure 13.17 Base Timer Reset operation by INT1
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
RST4
Base timer
(1)
≤ m ≤ 0FFFE
16
≤ m ≤ 0FFFE
16
m - 2
m - 2
/INT1
page 155
f o
4
5
8
m - 2
m - 1
m
m + 1 0000
m
16
or 0BFFF
≤ m ≤ 0FFFE
16
16
16
m - 1
m
m + 1 0000
m
m - 1
m
m + 1 0000
________
_______
13. Timer S
0001
16
16
0001
16
16
0001
16
16
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