X30 Read Sequence; Pll Clocking; Standby Mode And Headset Clamps; Detection Sequence From Wake - Cirrus Logic CS42L42 Manual

Example 5-4. SoundWire Power-Down Sequence (Cont.)
S T
TEP ASK
13 Confirm device is ready for
clock stop. Read SCP Control.
Repeat until CLOCK_STOP_
NOT_FINISHED is 0.
14 Send clock stop now
15 The master sends a stopping frame and stops SWIRE_CLK at the frame boundary at the end of that frame.
5.4 Page 0x30 Read Sequence
The following sequence is required to read from Page 0x30:
1. Power up Page 0x30 by clearing bit 7 of register 0x1102.
2. Enable Page 0x30 reads by writing the value 0x01 to register 0x1801.
3. Perform the read from Page 0x30.

5.5 PLL Clocking

Data-path logic is in the MCLK domain, where SCLK is expected to be 12 or 24 MHz. For clocking scenarios where ASP_
SCLK is neither 12 nor 24 MHz, the PLL must be turned on to provide the desired internal MCLK. At startup, the system
sets the SCLK bypass as default mode and switches to PLL output after it settles. PLL start-up time is a maximum of 1 ms.

5.6 Standby Mode and Headset Clamps

When the CS42L42 enters Standby Mode, headset clamps must first be

5.7 Detection Sequence from Wake

Ex. 5-5 is the procedure for implementing automatic headset-type detection from Standby Mode. Following a wake event,
the system responds to the WAKE being asserted, the INT pin being asserted, or both (depending on WAKE/INT
configuration) by taking the audio device out of Standby Mode, as shown in Steps 1–9.
Example 5-5. Headset Type and Load-Detection Sequence
S T
TEP ASK
1 Apply all relevant power supplies to the codec.
2 Apply a 12.0000-MHz signal to the MCLK input.
3 Enable the MCLK .
INT
4 Make WAKE inactive.
5 Set EVENT_STATUS_SEL to bring
values stored in VP domain
registers into VD_FILT domain
registers.
6 Wait 2 s.
DS1083F2
R /B F
EGISTER IT
SCP Control (Section 7.1.3) 0x0044
FORCE_RESET
CURRENT_BANK
Reserved
CLOCK_STOP_NOW
CLOCK_STOP_NOT_FINISHED
SCP Control (Section 7.1.3) 0x0044
FORCE_RESET
CURRENT_BANK
Reserved
CLOCK_STOP_NOW
CLOCK_STOP_NOT_FINISHED
R /B F
EGISTER IT IELDS
. 0x1009
MCLK Control
Reserved
INTERNAL_FS
Reserved
Wake Control. 0x1B71
M_MIC_WAKE ††
M_HP_WAKE ††
WAKEB_MODE ††
—
WAKEB_CLEAR
Mic Detect Control 1. 0x1B75
LATCH_TO_VP
EVENT_STATUS_SEL
HS_DETECT_LEVEL
V
IELDS ALUE
0x00
0
0
00 00
0
0
0x02
0
0
00 00
1
0
disabled—HS_CLAMP_DISABLE
V
ALUE
0x00
0000 00 —
0 Internal sample rate is MCLK
0 —
0xC0
Mask mic button detect wake
1
1 Mask HP detect wake.
0 WAKE latched low after a trigger event.
0 0400 Reserved
0 Normal operation.
0x5F
0 Enable setting of VP sticky status latches.
1 Sticky processed status events are selected.
01 1111 Detect percentage is set to default specified level.
5.4 Page 0x30 Read Sequence
D
ESCRIPTION
No action
Current register bank is Bank 0
—
Normal operation
Ready for clock stop
No action
Current register bank is Bank 0
—
Clock stops after one more frame.
Ready for clock stop.
= 1, see
D
ESCRIPTION
/250.
INT
.
CS42L42
p. 136.
97