Cirrus Logic CS42L42 Manual page 64

4.8.15 Configuration Guidelines with Examples
Ex. 4-3 and Ex. 4-4 describe configurations for programming three data ports for 48- and 96-kHz operations, each with
24-bit data. Data Port 1 has one 24-bit channel; Data Ports 2 and 3 have two channels each.
frame structure, with details for each port (HSTART, HSTOP, OFFSETS, and WORD_LENGTH). For each data port,
registers are programmed to indicate the location in the SoundWire frame where each payload data is stored. Each port
must be configured with a location such that its payload location does not overlap another port. The SoundWire master
must also be configured with the same settings for each port.
Parameter
WORD_LENGTH
HSTART
HSTOP
OFFSET1
OFFSET2
Offset (combined)
SAMPLE_INTERVAL_LOW
SAMPLE_INTERVAL_HIGH
Sample Interval
1.WORD_LENGTH is the number of bits in each channel minus 1.
Both examples have the same configuration—SoundWire clock = 12.288 MHz, 64 rows, 8 columns, 512 bits per frame,
SoundWire frame rate = 48 kHz.
Configuration details are summarized in
The WORD_LENGTH is the number of bits minus 1 in each channel's sample per port.
The HSTART and HSTOP values define the payload transport window, the columns in the SoundWire frame that bound
the port's payload data. Both examples set HSTART = 1 and HSTOP = 7, so that the payload data is in Columns 1–7. To
avoid overlap with the control word, Column 0 is not included.
The OFFSETx fields define the number of bits within the payload transport window that the start of the sample is delayed
from the sample interval boundary. Each port has a different offset to avoid overlap. Note that this example uses the
Block-per-Port Mode. The definition of the offset registers would change if Block-per-Channel Mode were used.
Although spaces appear between each port's payload, shown in different colors in
Both examples start with the SoundWire frame rate set to 48 kHz. Using a 12.288-MHz SoundWire clock, a 64 x 8 frame
yields a 48-kHz SoundWire frame rate. Setting the sample interval (the time in units of bit slots defining the rate at which
the port's data samples are transferred) to match the SoundWire frame rate, as shown in
interval. There are two bit slots per SoundWire clock cycle. Other sample interval rates can be multiplied or divided from
this sample rate without changing the same SoundWire frame rate.
Note the following:
• The sample interval and the frame can have different lengths.
• The sample interval must be a multiple or divide factor from the SoundWire frame length. Note that this does not
have to be an integer multiple, but rather a common multiple, where periodically the SoundWire frame boundary
aligns to the sample interval boundary. The SSP is the point at which all sample interval boundaries of all ports in
the system align to the same SoundWire frame boundary.
• Each port can have a different sample interval.
The sample interval is calculated in units of bit slots according to the following formula:
Sample Interval = 256 * SAMPLE_INTERVAL_HIGH + SAMPLE_INTERVAL_LOW + 1.
Setting SAMPLE_INTERVAL_HIGH = 1 and SAMPLE_INTERVAL_LOW = 255 results in a sample interval for a 48-kHz
frame at 12.288 MHz of 512 bit slots. Note that this also coincides with a frame size of 64 x 8 = 512.
DS1083F2
Example 4-3. Sample Interval Rate: 48 kHz
Data Port 1 Data Port 2
1
23 23
1 1
7 7
0 28
0 0
0 28
255 255
1 1
512 512
Ex. 4-3 and
Example 4-4. Sample Interval Rate: 96 kHz
Data Port 3 Data Port 1
23
1
7
84
0
84
255
1
512
Ex. 4-4.
4.8 SoundWire Interface
Fig. 4-29 shows the resulting
Data Port 2
23 23
1 1
7 7
0 28
0 0
0 28
255 255
0 0
256 256
Fig. 4-29, that spacing is not required.
Ex. 4-3, yields a 48-kHz sample
CS42L42
Data Port 3
23
1
7
84
0
84
255
0
256
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