Cirrus Logic CS42L42 Manual page 30

• Analog outputs. The analog output block, described in
Class H amplifiers. An on-chip step-down/inverting charge pump creates a positive and negative voltage equal to the
input or to either one-half or one-third of the input supply for the amplifiers, allowing an adaptable, full-scale output
swing centered around ground. The resulting internal amplifier supply can be ±VCP/3, ±VCP/2, ±VCP, or ±2.5 V.
The inverting architecture eliminates the need for large DC-blocking capacitors and allows the amplifier to deliver
more power to HP loads at lower supply voltages. The step-down architecture allows the amplifier's power supply
to adapt to the required output signal. This adaptive power-supply scheme converts traditional Class AB amplifiers
into more power-efficient Class H amplifiers.
• Class H amplifier. The HP output amplifiers, described in
Class H technology that maintains high performance and maximizes operating efficiency of a typical Class AB
amplifier.
• Clocking architecture. Described in
integrated fractional-N PLL using ASP_SCLK/SWIRE_CLK as the source clock or the internal PLL can be bypassed
and derived directly from the ASP_SCLK/SWIRE_CLK input pin.
• MIPI-compliant two-wire SoundWire interface. The CS42L42 integrates a SoundWire interface to transport audio
and control data, which provides an alternative to the I
• Serial ports. The CS42L42 has two serial data-port options: The TDM/I
port; the MIPI-compliant SoundWire serial port can be selected to communicate audio and voice data to and from
other devices in the system, such as application processors and Bluetooth
The ASP can operate in TDM Mode, which includes full-duplex communication, defeatable SDOUT driver for
sharing the TDM bus between multiple devices, flexible data structuring via control port registers, clock slave mode,
and higher bandwidth, enabling more data to be transferred to and from the device.
• S/PDIF Tx Port. The S/PDIF output port, described in
encoded (e.g., AC3) or PCM data from the serial audio ports to an external optical driver.
• Sample-rate converters (SRCs). SRCs, described in
serial ports within the digital-processing core. SRCs are used for the ASP output channel, and both ASP input
channels, the SoundWire output channel and both SoundWire input channels. SRCs can be bypassed. Note that
the S/PDIF channels do not have SRCs in their paths.
• Headset interface. This interface is described in
intelligent interface to an external headset. It also communicates with an applications processor to relay command
and status information. Headset-type detection is described in
• The CS42L42 supports plug presence-detect capability via the two associated sense pins: TIP_SENSE and RING_
SENSE. The sense pins are debounced to filter out brief events before being reported to the corresponding
presence detect bit and generating an interrupt if appropriate. Plug presence detection is described in
• Power management. Several control registers provide independent power-down control of the analog and digital
sections of the CS42L42, allowing operation in select applications with minimal power consumption. Power
management considerations are described in
• Control-port operation. The control port, described in
the codec. The control port operation may be completely asynchronous with respect to the audio sample rates. To
avoid potential interference problems, control-port data pins must remain static if no operation is required.
• Resets. Section 4.17
reset mechanism.
• Interrupts. The CS42L42 includes an open-drain interrupt output, INT. Interrupt mask registers control whether an
event associated with an interrupt status/mask bit pair triggers the assertion of INT.A set of SoundWire interrupts is
provided that is separate from the general interrupt implementation. See
DS1083F2
Section 4.7, the clock for the device can be supplied internally from an
Section
describes the reset options—power-on reset (POR), asserting RESET, and the SoundWire
Section 4.4, includes separate pseudodifferential headphone
Section 4.6, use a patented Cirrus Logic four-mode
2 C/ASP interfaces. See
2 S (ASP) port is a highly configurable serial
4.10, is integrated to provide a pass-through of
Section
Section 4.11, are used to bridge different sample rates at the
Section 4.12. It is a collection of low-power circuits that provide an
Section 4.13.
4.15.
Section 4.16, provides access to the registers for configuring
Section
4 Functional Description
Section 4.8.
® transceivers. See Section
4.18.
CS42L42
4.9.
Section 4.14.
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