Cirrus Logic CS42L42 Manual page 122

7.1.17 Memory Access Status
7
Default
0
Bits Name
7:4 — Reserved
3 LAST_LATE Last command late. Indicates whether the previous read command completed in time for the response to be included in a
single command for direct access. If not, indirect access procedures are required for registers.
This bit is cleared at the start of a new transaction through the APB interface.
0 (Default) Previous APB read access was direct.
1 Previous APB read access did not complete in time, and indirect access procedures are required.
Note: This bit is also used to set INT_STAT_LATE_RESP.
2 CMD_IN_ Command in progress. Indicates whether a read/write operation is in progress across the internal bus bridge, including
PROGRESS register access initiated through the control word.
Note: Applies only to read access through the internal bus bridge (address 0x1000 and above). Does not apply to
internal SoundWire registers (0x0000–0x0FFF).
0 (Default) No transfer is in progress across the bridge.
1 A read or write access is in progress across the bridge.
1 CMD_DONE Transfer done. Indicates whether the previous read/write access initiated by a control word command through the internal
memory bridge completed. It is cleared at the beginning of the next access attempt to the bridge (address above 0x1000).
CMD_DONE is cleared by any control word–initiated read/write to any address accessed through the internal memory
bridge. CMD_DONE is cleared on a read command that returns previously fetched data.
0 (Default) Previous access through the bridge not completed or no access requested yet.
1 Previous access through the bridge completed.
0 RDATA_ Read data ready. Indicates whether the previous control word–initiated read access is complete and the read data would
RDY
be returned on the next control word initiated read of the same address, which is preserved in MEM_READ_LAST_ADDR.
Note: Applies only to read access through the internal bus bridge (address 0x1000 and above) and not to internal
SoundWire registers (0x0000–0x0FFF). This bit is cleared by any control word–initiated read access to any address
accessed through the internal memory bridge.
0 (Default) Bridge does not contain previous read data or new read data fetch is in progress.
1 Bridge contains read data that can be read from the memory read data register (see
7.1.18 Memory Access Control
7
Default 0
Bits Name
7:2 — Reserved
1:0 LATE_ Late response. Selects the command response supplied in the control word NAK/ACK bits for read instructions when read data
RESP is not available in time to be returned in the same command.
00 Respond with COMMAND_IGNORED
01 (Default) Respond with COMMAND_OK, which allows for indirect access. If indirect access procedures are required to
access the read data at a later time in the MEM_READ_DATA, this selection allows the COMMAND_OK to acknowledge
that the internal access was accepted and initiated.
10 Respond with COMMAND_FAIL
11 Reserved
If operating conditions require direct access to always be allowed, the response can be programmed as either COMMAND_
IGNORED or COMMAND_FAIL to provide an immediate indication of the delay.
Note: A COMMAND_FAIL response can also be returned on APB access if the previous access did not complete.
DS1083F2
6 5
—
—
0 0
6 5
—
—
0 0
7.1 SoundWire Control Port 0 Registers
4 3
LAST_LATE CMD_IN_PROGRESS
0 0
Description
4 3
0 0
Description
CS42L42
Address Base + 0xD0
2 1
CMD_DONE RDATA_RDY
R/O
0 0
Section 7.1.21)
Address Base + 0xD1
2 1
LATE_RESP
R/W
0 0
0
0
0
1
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