Cirrus Logic CS42L42 Manual page 96

Example 5-4. SoundWire Power-Down Sequence (Cont.)
S T
TEP ASK
3 Deprepare Ports 1–3
3.1 Write Port 1–14 Prepare
Control
3.2 Read Port 1 Prepare
Status. Repeat until
value is 0x00.
3.3 Read Port 2 Prepare
Status. Repeat until
value is 0x00.
3.4 Read Port 3 Prepare
Status. Repeat until
value is 0x00.
4 Power down S/PDIF
transmitter.
5 Power down the HP, ADC, and
mixer.
6 Power down the ASP and
SRC.
7 Power down the codec.
8 Read PDN_DONE to confirm
that the codec is completely
powered down. Repeat until
value is 0x01
9 Discharge the capacitor
attached to the FILT+ pin.
10 Configure switch from SCLK to
RCO.
11 Confirm RCO is powered up.
Read the Oscillator Switch
Status and repeat until the
value reaches 0x05.
12 Prepare for clock stop now
DS1083F2
R /B F
EGISTER IT
DP1–14 Prepare Control 0x0F05
Reserved
PREPARE_CHANNEL2
PREPARE_CHANNEL1
DP1 Prepare Status (Section 7.2.5). 0x0104
Reserved
NOT_FINISHED_CHANNEL1
DP2 Prepare Status (Section 7.2.5). 0x0204
Reserved
NOT_FINISHED_CHANNEL2
NOT_FINISHED_CHANNEL1
DP3 Prepare Status (Section 7.2.5). 0x0304
Reserved
NOT_FINISHED_CHANNEL2
NOT_FINISHED_CHANNEL1
S/PDIF Control 1. 0x2801
Reserved
SPDIF_TX_RAW
SPDIF_TX_KAE
SPDIF_TX_PDN
Power Down Control 1. 0x1101
ASP_DAO_PDN
ASP_DAI_PDN
MIXER_PDN
EQ_PDN
HP_PDN
ADC_PDN
Reserved
PDN_ALL
Power Down Control 2. 0x1102
Reserved
DISCHARGE_FILT+
SRC_PDN_OVERRIDE
ASP_DAI1_PDN
DAC_SRC_PDNB
ADC_SRC_PDNB
Power Down Control 1. 0x1101
ASP_DAO_PDN
ASP_DAI_PDN
MIXER_PDN
EQ_PDN
HP_PDN
ADC_PDN
Reserved
PDN_ALL
Codec Interrupt Status. 0x1308
Reserved
HSDET_AUTO_DONE
PDN_DONE
Power Down Control 2. 0x1102
Reserved
DISCHARGE_FILT+
SRC_PDN_OVERRIDE
ASP_DAI0_PDN
DAC_SRC_PDNB
ADC_SRC_PDNB
Oscillator Switch Control. 0x1107
Reserved
SCLK_PRESENT
Oscillator Switch Status. 0x1109
Reserved
OSC_PDNB_STAT
OSC_SW_SEL_STAT
SCP System Control (Section 7.1.4) 0x0045
Reserved
WAKE_UP_ENABLE
CLOCK_STOP_MODE
Reserved
CLOCK_STOP_PREPARE
V
IELDS ALUE
0x00
0000 00
0
0
0x00
0000 000
0
0x00
0000 00
0
0
0x00
0000 00
0
0
0x01
0000 0
0
0
1
0xFE
1
1
1
1
1
1
1
0
0x8C
100
0
1
1
0
0
0xFF
1
1
1
1
1
1
1
1
0x01
0000 00
0
1
0x9C
100
1
1
1
0
0
0x00
0000 000
0
0x05
0000 0
1
01
0x01
0000
0
0
0
1
5.3 SoundWire Power Sequences
D
ESCRIPTION
—
Channel deactivated
Channel deactivated
—
Channel finished
—
Channel finished
Channel finished
—
Channel finished
Channel finished
Reserved
S/PDIF outputs 24-bit data with control info
Don't care
Power down S/PDIF transmitter
ASP output path powered down
ASP SDOUT input path is powered down
Mixer is powered down
Equalizer powered down
HPOUT powered down
ADC powered down
—
Codec powered up
—
FILT+ is not clamped to ground.
SRC is powered down.
ASP is powered down.
DAC SRC is powered down.
ADC SRC is powered down.
ASP output path is powered down.
ASP input path is powered down.
Mixer is powered up.
Equalizer powered down
HPOUT powered up.
ADC powered up.
—
Codec powered up.
—
HS detection is disabled or incomplete.
Power-down done.
—
FILT+ is clamped to ground.
SRC is powered down.
ASP is powered down.
DAC SRC is powered down.
ADC SRC is powered down.
—
SCLK not present
—
RCO powered up
RCO selected for internal MCLK
—
Asynchronous wake disabled.
Slave must not lose context in Clock Stop Mode.
—
The CS42L42 is notified to prepare for clock stop.
CS42L42
96