Cirrus Logic CS42L42 Manual page 77

The interface generates HSBIAS, a programmable ultrahigh PSRR headset bias output for an external microphone. A
low-voltage headset bias supply (VP = 3.0–3.2 V range) mode is supported. Signaling to the headset to set its operating
voltage is facilitated via the bias output
Audible transients that would occur as certain headset plugs are unplugged are minimized by using the headset bias Hi-Z
feature Split digital-power domains (VD_FILT and VP) within the headset interface support an ultralow-power standby
mode where only the VP supply is used. An output signal may be used to tell the system to wake from its low-power state
when a headset plug is inserted or removed or a mic short event (S0 button press) occurs. The interface may be reset by
three types of resets with progressively less effect.
HSBIAS_FILT
TIP_SENSE
HS_DETECT
HS_DETECT_REF
The control port includes registers that source individually maskable interrupts. Event-change debouncing is used to filter
applicable status registers. Shadow registering can record multiple events allowing for less frequent register reading.
Latchable duplicate registers are used to pass information to the Standby Mode supply domain.
Notes:
• If HSBIAS is Hi-Z, the headset interface is in an invalid mode.
• PDN_ALL must not be set if any of this following is true:
—Normal Mode is selected (DETECT_MODE ≠ 00).
—Mic DC-level detection is enabled
—HS bias sense detection is enabled
DS1083F2
VA
VA
HSBIAS
LDO
Regulator
Headphone
Detect
+
–
Short
Threshold
Reference
Step-Down,
Inverting
Charge
Pump
–VCP_FILT
Figure 4-42. Headset Interface Block Diagram
(PDN_MIC_LVL_DETECT
(HSBIAS_SENSE_EN
VP VD_FILT
VP VD_FILT
LDO Regulator
Headset Interface
Digital
Detect Level Setting Comparator
–
DC
Detection
+
ADC
Detection
Decode
Logic
+
–
S0
Detection
RESET
RESET
Soft
Reset
GND
–VCP_FILT GND
= 0; see
= 1; see
4.12 Headset Interface
VL
and POR
Generator
Power On Reset
WAKE
Logic
INT
RESET
Control
Port
Control Port
VL
p. 150).
p. 148).
CS42L42
77