5. Set
LATCH_TO_VP
6. Set
HSBIAS_CTRL
7. Set
ADPTPWR
= 100 (see
8. Set the analog soft-ramp rate
9. Set the digital soft-ramp rate (DSR_RATE; see
10.After load detection completes, ASR_RATE, DSR_RATE, ADPTPWR, and DAC_HPF_EN must be restored to
their previous values. See
See the detailed detection instruction sequence in
After an HP-detect event, if
capacitance of the output load. A 24-kHz tone is output on HPOUTA, and HS3 or HS4 (depending on China headset detect
results) is measured using an internal resistor bank as a reference.
RLA_STAT
(see
p.
148) reports resistance-detection results for Channel A as follows:
00: 15
•
01: 30
•
•
10: 3 k
•
11: Reserved
If the typical output resistance of less than ~300 is indicated, a low-capacitance load is assumed. If the resistance is
greater than 300 capacitance detection proceeds. After the detection sequence completes,
148) is set. The results of capacitor detection is reported in
p.
the value in HPOUT_LOAD(see
Notes:
• The HP path must be powered down before updating the HPOUT_LOAD setting and repowered afterwards.
• Low capacitance results were determined with C
4.4.5
Slow Start Control
Mixer, DAC, and HP soft ramping is enabled through
to DAC/HP volumes are applied slowly by stepping through each volume-control setting with a delay between steps equal
to an integer number of Fs periods. The delay between steps, which can vary from 1/Fs to 72/Fs periods, is set via
RATE
and
ASR_RATE
(see
If ramping is disabled, changes occur immediately with the clock edge.
4.5 System Headphone Parasitic Resistances
Parasitic resistances limit the measurements on several specs, including the following:
•
Headphone-to-analog input isolation
•
Headphone interchannel isolation
•
Headphone mute attenuation
•
Headphone DC offset
DS1083F2
(see
p.
150).
to 00 (Hi-Z Mode; see
p.
150).
p.
155).
(ASR_RATE
= 0111; see
Section 4.6
for details.
Ex. 5-5
HP_LD_EN
is set (see
p.
154), which determines the compensation of the headphone amplifier.
p.
p.
129).
4.5 System Headphone Parasitic Resistances
p.
129).
p.
129) = 0001.
for details.
148), the CS42L42 proceeds to detect the resistance and
CLA_STAT
(see
p.
= 1 nF; high capacitance results were determined with C
L
SLOW_START_EN (p.
129). If SLOW_START_EN = 111, changes
HPLOAD_DET_DONE
148). This result can be used to program
CS42L42
(see
= 10 nF.
L
DSR_
39
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