Cirrus Logic CS42L42 Manual page 91

Example 5-1. Power-Up Sequence (Cont.)
S T
TEP ASK
5 Enable SCLK.
6 Enable the ASP receiver
channels.
7 Configure the DAC.
8 Configure the appropriate volume controls and DAC source selects.
8.1 Set Mixer A input to
0 dB.
8.2 Mute the mixer ADC
input
8.3 Set Mixer B input to
0 dB.
9 Configure the HP control.HP Control. 0x2001
10 Power up the codec
11 The headphone amplifier is operational after 10 ms.
DS1083F2
R /B F
EGISTER IT
ASP Clock Configuration 1. 0x1207
Reserved
ASP_SCLK_EN
ASP_HYBRID_MODE
ASP_SCPOL_IN_ADC
ASP_SCPOL_IN_DAC
ASP_LCPOL_OUT
ASP_LCPOL_IN
ASP Receive Enable. 0x2A01
ASP_RX1_CH_EN
ASP_RX0_CH_EN
ASP_RX1_2FS
ASP_RX0_2FS
DAC Control 1. 0x1F01
Reserved
DACB_INV
DACA_INV
Mixer Channel A Input Volume. 0x2301
Reserved
MIXER_CHA_VOL
Mixer ADC Input Volume. 0x2302
Reserved
MIXER_ADC_VOL
Mixer Channel B Input Volume. 0x2303
Reserved
MIXER_CHB_VOL
Reserved
ANA_MUTE_B
ANA_MUTE_A
FULL_SCALE_VOL
Reserved
Power Down Control 1. 0x1101
ASP_DAO_PDN
ASP_DAI_PDN
MIXER_PDN
EQ_PDN
HP_PDN
ADC_PDN
Reserved
PDN_ALL
V
IELDS ALUE
0x20
00
1
0
0
0
0
0
0x3C
00
11 11
0
0
0x00
0000 00
0
0
0x00
00
00 0000
0x3F
00
11 1111
0x00
00
00 0000
0x03
0000
0
0
1
1
0x96
1
0
0
1
0
1
1
0
5.1 Power-Up Sequence
D
ESCRIPTION
—
ASP SCLK enabled.
LRCK is an input generated from SCLK.
SCLK input drive polarity for ADC is normal.
SCLK input drive polarity for DAC is normal.
LRCK output drive polarity is normal.
LRCK input polarity (pad to logic) is normal.
RX1 buffer is disabled.
RX0 buffer is enabled.
ASP DAI1 is standard sample rate.
ASP DAI0 is standard sample rate.
—
DACA signal not inverted.
DACB signal not inverted.
—
Input A is set to 0 dB.
—
Mixer ADC input is muted.
—
Input B is set to 0 dB.
—
Channel B is unmuted.
Channel A is unmuted.
Full-scale volume is -6dB for headphone output.
—
ASP output path is powered down.
ASP input path is powered up.
Mixer is powered up.
Equalizer powered down
HPOUT powered up.
ADC powered down.
—
Codec powered up.
CS42L42
91