Cirrus Logic CS42518-DQZ System Manuals

Manuals and User Guides for Cirrus Logic CS42518-DQZ System. We have 2 Cirrus Logic CS42518-DQZ System manuals available for free PDF download: Manual, Instructions Manual

Cirrus Logic CS42518-DQZ Manual (91 pages)

110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

Brand: Cirrus Logic | Category: Conference System | Size: 1.58 MB

Table of Contents
2
1 Characteristics and Specifications

7
2 Pin Descriptions

17
3 Typical Connection Diagram

20
- Figure 5. Typical Connection Diagram
  20
4 Applications

21
- Overview
  21
- Analog Inputs
  21
- Analog Outputs
  22
- S/PDIF Receiver
  24
- Clock Generation
  25
- Digital Interfaces
  27
- Control Port Description and Timing
  38
- Interrupts
  40
- Reset and Power-Up
  40
- Power Supply, Grounding, and PCB Layout
  40
5 Register Quick Reference

42
6 Register Description

47
7 Parameter Definitions

73
8 References

74
9 Package Dimensions

75
- Thermal Characteristics
  75
10 Appendix A: External Filters

76
11 Appendix B: S/Pdif Receiver

77
12 Appendix C: Pll Filter

80
- Figure 27. PLL Block Diagram
  80
  - External Filter Components
    81
    
    General
    81
    
    Jitter Attenuation
    81
    
    Figure 28. Jitter Attenuation Characteristics of PLL
    81
    
    Table 21. PLL External Component Values
    81
    
    Capacitor Selection
    82
    
    Circuit Board Layout
    82
    
    Figure 29. Recommended Layout Example
    82
13 Appendix D: External Aes3/Spdif/Iec60958 Receiver Components

83
14 Appendix E: Adc Filter Plots

84
15 Appendix F: Dac Filter Plots

86

Cirrus Logic CS42518-DQZ Instructions Manual (87 pages)

110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

Brand: Cirrus Logic | Category: Receiver | Size: 1.76 MB

Table of Contents
2
Characteristics and Specifications
7
Specified Operating Conditions
7
Absolute Maximum Ratings
7
Analog Input Characteristics
8
A/D Digital Filter Characteristics
9
Analog Output Characteristics
10
D/A Digital Filter Characteristics
11
Switching Characteristics
12
Figure 1. Serial Audio Port Master Mode Timing
12
Figure 2. Serial Audio Port Slave Mode Timing
12
Switching Characteristics - Control Port - I2C Format
13
Figure 3. Control Port Timing - I2C Format
13
Switching Characteristics - Control Port - Spi Format
14
Figure 4. Control Port Timing - SPI Format
14
DC Electrical Characteristics
15
Digital Interface Characteristics
15
Pin Descriptions
16
Typical Connection Diagrams
19
Figure 5. Typical Connection Diagram
19
Figure 6. Typical Connection Diagram with PLL
20
Applications
21
Overview
21
Analog Inputs
21
Line Level Inputs
21
Figure 7. Full-Scale Analog Input
21
High Pass Filter and DC Offset Calibration
22
Analog Outputs
22
Line Level Outputs and Filtering
22
Interpolation Filter
22
Figure 8. Full-Scale Output
22
Digital Volume and Mute Control
23
ATAPI Specification
23
Figure 9. ATAPI Block Diagram (X = Channel Pair 1, 2, 3, 4)
23
S/PDIF Receiver
24
8:2 S/PDIF Input Multiplexer
24
Error Reporting and Hold Function
24
Channel Status Data Handling
24
User Data Handling
24
Non-Audio Auto-Detection
24
Clock Generation
25
PLL and Jitter Attenuation
25
Figure 10. CS42518 Clock Generation
25
OMCK System Clock Mode
26
Master Mode
26
Slave Mode
26
Table 2. Common OMCK Clock Frequencies
26
Table 3. Common PLL Output Clock Frequencies
26
Digital Interfaces
27
Serial Audio Interface Signals
27
Table 4. Slave Mode Clock Ratios
27
Table 5. Serial Audio Port Channel Allocations
27
Serial Audio Interface Formats
29
Figure 11. I 2 S Serial Audio Formats
29
Figure 12. Left Justified Serial Audio Formats
30
Figure 13. Right Justified Serial Audio Formats
30
Figure 14. One Line Mode #1 Serial Audio Format
31
Figure 15. One Line Mode #2 Serial Audio Format
31
ADCIN1/ADCIN2 Serial Data Format
32
Figure 16. ADCIN1/ADCIN2 Serial Audio Format
32
One Line Mode(OLM) Configurations
33
OLM Config #1
33
Figure 17. OLM Configuration #1
33
OLM Config #2
34
Figure 18. OLM Configuration #2
34
OLM Config #3
35
Figure 19. OLM Configuration #3
35
OLM Config #4
36
Figure 20. OLM Configuration #4
36
OLM Config #5
37
Figure 21. OLM Configuration #5
37
Control Port Description and Timing
38
SPI Mode
38
Figure 22. Control Port Timing in SPI Mode
38
I2C Mode
39
Figure 23. Control Port Timing, I2C Write
39
Figure 24. Control Port Timing, I2C Read
39
Interrupts
40
Reset and Power-Up
40
Power Supply, Grounding, and PCB Layout
40
Register Quick Reference
42
Register Description
46
Memory Address Pointer (MAP)
46
Chip I.D. and Revision Register (Address 01H) (Read Only)
46
Power Control (Address 02H)
47
Functional Mode (Address 03H)
47
Table 6. DAC De-Emphasis
48
Interface Formats (Address 04H)
49
Table 7. Receiver De-Emphasis
49
Table 8. Digital Interface Formats
49
Table 9. ADC One-Line Mode
50
Table 10. DAC One-Line Mode
50
Misc Control (Address 05H)
51
Clock Control (Address 06H)
52
Table 11. RMCK Divider Settings
52
Table 12. OMCK Frequency Settings
53
Table 13. Master Clock Source Select
53
OMCK/PLL_CLK Ratio (Address 07H) (Read Only)
54
RVCR Status (Address 08H) (Read Only)
54
Table 14. AES Format Detection
54
Burst Preamble PC and PD Bytes (Addresses 09H - 0Ch)(Read Only)
55
Table 15. Receiver Clock Frequency Detection
55
Volume Transition Control (Address 0Dh)
56
Channel Mute (Address 0Eh)
58
Volume Control (Addresses 0Fh, 10H, 11H, 12H, 13H, 14H, 15H, 16H)
58
Channel Invert (Address 17H)
58
Table 16. Example Digital Volume Settings
58
Mixing Control Pair 1 (Channels A1 & B1)(Address 18H)
59
Mixing Control Pair 2 (Channels A2 & B2)(Address 19H)
59
Mixing Control Pair 3 (Channels A3 & B3)(Address 1Ah)
59
Mixing Control Pair 4 (Channels A4 & B4)(Address 1Bh)
59
Table 17. ATAPI Decode
60
ADC Left Channel Gain (Address 1Ch)
61
ADC Right Channel Gain (Address 1Dh)
61
Receiver Mode Control (Address 1Eh)
61
Table 18. Example ADC Input Gain Settings
61
Receiver Mode Control 2 (Address 1Fh)
62
Table 19. TXP Output Selection
62
Interrupt Status (Address 20H) (Read Only)
63
Table 20. Receiver Input Selection
63
Interrupt Mask (Address 21H)
64
Interrupt Mode MSB (Address 22H) Interrupt Mode LSB (Address 23H)
64
Channel Status Data Buffer Control (Address 24H)
65
Receiver Channel Status (Address 25H) (Read Only)
65
Receiver Errors (Address 26H) (Read Only)
66
Table 21. Auxiliary Data Width Selection
66
Receiver Errors Mask (Address 27H)
68
Mutec Pin Control (Address 28H)
68
Rxp/General Purpose Pin Control (Addresses 29H to 2Fh)
69
Q-Channel Subcode Bytes 0 to 9 (Addresses 30H to 39H) (Read Only)
70
C-Bit or U-Bit Data Buffer (Addresses 3Ah to 51H) (Read Only)
70
Parameter Definitions
71
References
72
Package Dimensions
73
Thermal Characteristics
73
Appendix A: External Filters
74
ADC Input Filter
74
DAC Output Filter
74
Figure 25. Recommended Analog Input Buffer
74
Figure 26. Recommended Analog Output Buffer
74
Appendix B: S/Pdif Receiver
75
Error Reporting and Hold Function
75
Channel Status Data Handling
75
Channel Status Data E Buffer Access
76
One Byte Mode
76
Two Byte Mode
76
Figure 27. Channel Status Data Buffer Structure
76
Serial Copy Management System (SCMS)
77
User (U) Data E Buffer Access
77
Non-Audio Auto-Detection
77
Format Detection
77
Appendix C: Pll Filter
78
Figure 28. PLL Block Diagram
78
External Filter Components
79
General
79
Jitter Attenuation
79
Figure 29. Jitter Attenuation Characteristics of PLL
79
Table 22. PLL External Component Values
79
Capacitor Selection
80
Circuit Board Layout
80
Figure 30. Recommended Layout Example
80
Appendix D: External Aes3/Spdif/Iec60958 Receiver Components
81
AES3 Receiver External Components
81
Figure 31. Consumer Input Circuit
81
Figure 32. S/PDIF MUX Input Circuit
81
Figure 33. TTL/CMOS Input Circuit
81
Appendix E: Adc Filter Plots
82
Figure 34. Single Speed Mode Stopband Rejection
82
Figure 35. Single Speed Mode Transition Band
82
Figure 36. Single Speed Mode Transition Band (Detail)
82
Figure 37. Single Speed Mode Passband Ripple
82
Figure 38. Double Speed Mode Stopband Rejection
82
Figure 39. Double Speed Mode Transition Band
82
Figure 40. Double Speed Mode Transition Band (Detail)
83
Figure 41. Double Speed Mode Passband Ripple
83
Figure 42. Quad Speed Mode Stopband Rejection
83
Figure 43. Quad Speed Mode Transition Band
83
Figure 44. Quad Speed Mode Transition Band (Detail)
83
Figure 45. Quad Speed Mode Passband Ripple
83
Appendix F: Dac Filter Plots
84
Figure 46. Single Speed (Fast) Stopband Rejection
84
Figure 47. Single Speed (Fast) Transition Band
84
Figure 48. Single Speed (Fast) Transition Band (Detail)
84
Figure 49. Single Speed (Fast) Passband Ripple
84
Figure 50. Single Speed (Slow) Stopband Rejection
84
Figure 51. Single Speed (Slow) Transition Band
84
Figure 52. Single Speed (Slow) Transition Band (Detail)
85
Figure 53. Single Speed (Slow) Passband Ripple
85
Figure 54. Double Speed (Fast) Stopband Rejection
85
Figure 55. Double Speed (Fast) Transition Band
85
Figure 56. Double Speed (Fast) Transition Band (Detail)
85
Figure 57. Double Speed (Fast) Passband Ripple
85
Figure 58. Double Speed (Slow) Stopband Rejection
86
Figure 59. Double Speed (Slow) Transition Band
86
Figure 60. Double Speed (Slow) Transition Band (Detail)
86
Figure 61. Double Speed (Slow) Passband Ripple
86
Figure 62. Quad Speed (Fast) Stopband Rejection
86
Figure 63. Quad Speed (Fast) Transition Band
86
Figure 64. Quad Speed (Fast) Transition Band (Detail)
87
Figure 65. Quad Speed (Fast) Passband Ripple
87
Figure 66. Quad Speed (Slow) Stopband Rejection
87
Figure 67. Quad Speed (Slow) Transition Band
87
Figure 68. Quad Speed (Slow) Transition Band (Detail)
87
Figure 69. Quad Speed (Slow) Passband Ripple
87

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Cirrus Logic CS42518-DQZ System Manuals

Cirrus Logic CS42518-DQZ Manual (91 pages)

Table of Contents

1 Characteristics and Specifications

2 Pin Descriptions

3 Typical Connection Diagram

4 Applications

5 Register Quick Reference

6 Register Description

7 Parameter Definitions

8 References

9 Package Dimensions

10 Appendix A: External Filters

11 Appendix B: S/Pdif Receiver

12 Appendix C: Pll Filter

13 Appendix D: External Aes3/Spdif/Iec60958 Receiver Components

14 Appendix E: Adc Filter Plots

15 Appendix F: Dac Filter Plots

Cirrus Logic CS42518-DQZ Instructions Manual (87 pages)

Table of Contents

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