Cirrus Logic CS42L42 Manual page 69

Low-power audio codec with soundwire-i2s/tdm and audio processing
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FSYNC_PULSE_WIDTH_LB
which the LRCK signal is held high during each frame. Like the LRCK period, the LRCK-high width is programmable in
single SCLK periods, from at least one period to at most the LRCK period minus one. That is, the LRCK-high width must
be shorter than the LRCK period.
As shown in
Fig.
4-33, if 50/50 Mode is enabled
to the LRCK period divided by two (rounded down to the nearest integer when the LRCK period is odd). When the serial
port is in 50/50 Mode, setting the LRCK high duration to a value other than half of the period causes erroneous operation.
LRCK
Falling
Edge
SCLK
Rising
Edge
LRCK
Falling
Edge
SCLK
Rising
Edge
Fig. 4-34
shows how LRCK frame start delay (ASP_FSD, see
synchronization edge to the start of frame data.
FSD = 101
FSD = 100
FSD = 011
LRCK
FSD = 010
FSD = 001
FSD = 000
SCLK
SDIN/SDOUT
4.9.3
Channel Location and Resolution
Each serial-port channel's location and offset is configured through the registers in
in single SCLK-period resolution. If set to the minimum location offset, a channel sends or receives on the first SCLK period
of a new frame. Channel size is programmable in 8- to 32-bit byte resolutions. Note that only the S/PDIF port transmits up
to 32 bits. ADC and DAC ports are limited to 24 bits and truncate the 8 LSBs of a 32-bit audio stream.
DS1083F2
and
FSYNC_PULSE_WIDTH_UB
(ASP_5050
FSYNC_PULSE_WIDTH
...
...
...
Even FSYNC_PERIOD
FSYNC_PULSE_WIDTH
...
...
...
Odd FSYNC_PERIOD
Figure 4-33. ASP LRCK Period, High Width, 50/50 Mode
0
0.5
1
1.5
2
2.5
0
1
2
3
4
5
Channel location and resolution
Figure 4-34. LRCK Frame-Start Delay Example Diagram
(see
p.
137) control the number of SCLK periods for
= 1, see
p.
138), the LRCK high duration must be programmed
FSYNC_PERIOD
...
...
...
FSYNC_PERIOD
FSYNC_PULSE_WIDTH
...
...
...
p.
138) controls the number of SCLK periods from LRCK
...
...
...
...
...
...
...
...
6
7
8
9
N – 5
N – 4
4.9 Audio Serial Port (ASP)
FSYNC_PERIOD count clock is absent
N – 3
N – 2
N – 1
End of frame
Table
4-16. Location is programmable
CS42L42
69

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