Cirrus Logic CS42L42 Manual page 121

Bits Name
6:1 — Reserved
0 SCP_IMP_ SCP implementation defined 1. The combined interrupt from the interrupt controller is connected to this bit.
DEF1
0 (Default) Interrupt not asserted.
1 Interrupt condition asserted
7.1.14 General Interrupt Mask 1
7
Default
0
Bits Name
7:1 — Reserved
0 M_SCP_ Status bit interrupt enable 1. Enables corresponding status bit to generate an interrupt. This bit is cleared automatically on
IMP_ any internal reset or loss-of-frame synchronization.
DEF1
0 (Default) Corresponding status bit cannot generate an interrupt.
1 Corresponding status bit may generate an interrupt.
7.1.15 General Interrupt Status 2
7 6
Default
0 0
Bits Name
7:3 Reserved
—
2 INT_STAT_ Late response. Reports whether any SoundWire read command did not complete in time for the response to be included
LATE_RESP in the read data response of the same command. See
0 (Default) Interrupt not asserted
1 Interrupt condition detected. Set on an APB read that requires indirect-access procedures. The associated interrupt
can be used as a warning if direct access was expected, but indirect access was required. If set, the bit is cleared by
writing a 1 to the bit. It is not cleared by the sync loss reset.
1 INT_STAT_ Timeout error. Reports whether a timeout error occurs on the APB read or write access. Timeout error generation is
TIMEOUT_ controlled through the memory access timeout register.
ERR
0 (Default) Interrupt not asserted
1 Interrupt condition detected. If set, the bit is cleared by writing a 1 to the bit. It is not cleared by the sync loss reset.
0 — Reserved
7.1.16 General Interrupt Mask 2
7
Default
0
Bits Name
7:3 — Reserved
2 M_LATE_ Late response mask. Enables a late read data event to generate an generate an interrupt. This bit is automatically cleared
RESP on any internal reset or loss-of-frame synchronization.
0 (Default) Late read data does not generate an interrupt.
1 Late read data generates an interrupt.
1 M_ Timeout error mask. Enables an APB timeout error event to generate an interrupt
TIMEOUT_
0 (Default) Timeout error does not generate an interrupt.
ERR
1 Timeout error generates an interrupt.
0 Reserved
—
DS1083F2
6 5
0 0
5 4 3
—
—
0 0 0
6 5
—
—
0 0
7.1 SoundWire Control Port 0 Registers
Description
4 3
—
—
0 0
Description
2
INT_STAT_LATE_RESP INT_STAT_TIMEOUT_ERR
R/W1C
0
Description
Section 4.8.12.1 for details.
4 3
M_LATE_RESP M_TIMEOUT_ERR
0 0
Description
Address Base + 0xC1
2 1
M_SCP_IMP_DEF1
0 0
Address Base + 0xC2
1
R/W1C
0
Address Base + 0xC3
2 1
R/W R/W
0 0
CS42L42
0
R/W
0
0
—
—
0
0
—
—
0
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