Interrupt Registers - Cirrus Logic CS42L42 Manual

7.5.10 Input ASRC Clock Select
R/W
7
Default
0
Bits Name
7:2 — Reserved
1:0 CLK_IASRC_ Input ASRC clock select. Selects input ASRC MCLK
SEL 00 (Default) 6 MHz
7.5.11 Output ASRC Clock Select
R/W
7
Default
0
Bits Name
7:2 — Reserved
1:0 CLK_ Output ASRC clock select. Selects output ASRC MCLK
OASRC_SEL 00 (Default) 6 MHz
7.5.12 PLL Divide Configuration 1
R/W
7
Default 0
Bits Name
7:3 — Reserved
2 PLL_REF_ Invert PLL reference clock. See
INV
0 (Default) Normal
1 Inverted
1:0 SCLK_ PLL reference divide select. See
PREDIV 00 (Default) Divide by 1

7.6 Interrupt Registers

7.6.1 ADC Overflow Interrupt Status
R/O
7
Default
0
Bits Name
7:1 — Reserved
0 ADC_ ADC overflow. Indicates the overrange status in the corresponding signal path. Rising-edge state transitions may cause an
OVFL interrupt, depending on the programming of the associated interrupt mask bit.
0 No digital clipping has occurred in the data path of the respective signal source.
1 Digital clipping has occurred in the data path of the respective signal source.
7.6.2 Mixer Interrupt Status
R/O
7
Default 0
Bits Name
7:4 — Reserved
3 EQ_ Digital equalizer biquad overflow. Indicates the overrange status in the individual biquads in the equalizer data path.
BIQUAD_ Rising-edge state transitions may cause an interrupt, depending on the programming of the associated interrupt mask bit.
OVFL
0 No digital clipping occurred in one of the individual biquads in the equalizer data path
1 Digital clipping occurred in one of the individual biquads in the equalizer data path
DS1083F2
6 5
—
0 0
01 12 MHz
6 5
—
0 0
01 12 MHz
6 5
—
0 0
Table 4.7.3
Table 4.7.3
01 Divide by 2
6 5
0 0
6 5
—
0 0
4 3
0 0
Description
frequency. See
INT
10 24 MHz 11 Reserved
4 3
0 0
Description
frequency. See
INT
10 24 MHz
4 3
0 0
Description
for programming guidelines.
for programming guidelines.
10 Divide by 4
4 3
—
0 0
Description
4 3
EQ_BIQUAD_OVFL
0 x
Description
7.6 Interrupt Registers
2 1
CLK_IASRC_SEL
0 0
Section 4.11 for programming details.
2 1
CLK_OASRC_SEL
0 0
Section 4.11 for programming details.
11 Reserved
2 1
PLL_REF_INV SCLK_PREDIV
0 0
11 Divide by 8
2 1
0 0
2 1
EQ_OVFL MIX_CHA_OVFL MIX_CHB_OVFL
x x
CS42L42
Address 0x120A
0
0
Address 0x120B
0
0
Address 0x120C
0
0
Address 0x1301
0
ADC_OVFL
x
Address 0x1302
0
x
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