Cirrus Logic CS42L42 Manual page 47

4.7.1 Start-Up Clocking Using the RC Oscillator (RCO)
At power on, an integrated low-power RCO, shown in
CS42L42, during which time SCLK is unavailable. A reset event always returns it to running off of the RCO. If SCLK is
unavailable, RCO clocking must be used only for I
RCO is multiplexed with MCLK
be disabled before data conversion.
Note the following:
• OSC_SW_SEL_STAT
With the existing encoding, only one bit can physically change at a time, and the bit changing is always synchronous
to the clock that is currently selected.
• OSC_PDNB_STAT
• SCLK_PRESENT is used to determine the internal MCLK source. See
The clock-switch state machine uses the transition of SCLK_PRESENT to both initiate switches between the selected
internal MCLK between the SCLK pin (SCLK_PRESENT = 1) or the internal RCO (SCLK_PRESENT = 0) and to send the
C stop condition that each switching event requires. During switching, a delay of at least 150 S is needed before
2
I
additional successful I 2 C communication can begin to use the new clocking source.
Notes:
• Muting the system is recommended when a new clock source is chosen.
• For normal operation, SCLK—not RCO—must be used (SCLK_PRESENT = 1) for running the ASP data path.
4.7.1.1 Switching from RCO
With SCLK running, an SCLK_PRESENT 0-to-1 transition starts a switch from the RCO to the selected SCLK or PLL. This
switch is superseded by any outstanding I
150 s to complete, during which time the system requires that no new I
transaction can begin after this 150-s delay.
4.7.1.2 Switching to RCO
To stop SCLK, the system must revert to RCO clocking to ensure that I
the RCO back up, SCLK_PRESENT must be cleared before stopping SCLK. A 1-to-0 SCLK_PRESENT transition
generates a glitch-free mux switch timing from SCLK to RCO. SCLK must remain running during the transition and new
C transactions must not be initiated for at least 150 s after an I
2
I
begin until after this 150-s delay.
Failure to account for this could cause communications to fail.
4.7.2 MCLK Sources
INT
The MCLK source is supplied directly from ASP_SCLK/SWIRE_CLK input pin or from the fractional-N PLL. MCLKDIV
INT
must be set according to the MCLK
or the 24-MHz region (22.5792–24.576 MHz).
MCLK Source MCLK_SRC_SEL
INT
ASP_SCLK/
SWIRE_CLK
Fractional-N PLL
MCLK is switched through internal glitchless clock muxing. Doing so during operation may cause audible artifacts, but
INT
does not put the device into an unrecoverable state. Therefore, it is recommended to mute the system for at least 150 s.
DS1083F2
2 C functionality.
and fed to the I 2 C slave control port. The SCLK must become active and the RCO must
INT
(see p. 133) indicates the status of the clock switching (in transition, RCO, or SCLK/PLL).
(see p. 133) indicates the RCO power-down status.
2 C transactions. After the I
frequency, which must be set to either the 12-MHz region (11.2896–12.288 MHz)
INT
Table 4-6
Table 4-4. MCLK
(see p. 136) MCLKDIV
0
1
Fig. 4-20, functions as the default clock for the digital core of the
Section 7.4.6
2 C stop condition is sent, the transition begins, taking
2 C transactions be initiated. The next I
2 C communications function properly. To power
2
C stop is received. The next I
shows several examples.
Source Restrictions
INT
(see p. 136) Nominal ASP_SCLK/SWIRE_CLK Pin Frequency
0
1
0
1
CS42L42
4.7 Clocking Architecture
for details.
2
C transaction cannot
Table 4-4 lists further restrictions.
12 MHz
24 MHz
12 MHz
24 MHz
2 C
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