Sample-Rate Converters (Srcs) - Cirrus Logic CS42L42 Manual

X
M Channel 1
4.10.3.2 Subframe Format
Each subframe is divided into 32 time slots, numbered 0–31, as shown in
0
Preamble
4.10.3.3 Channel Coding
To minimize DC buildup on the transmission line, to facilitate clock recovery from the data stream, and to make the
interface insensitive to the polarity of connections, Time Slots 4–31 are encoded in biphase mark.
Each bit to be sent is represented by a symbol comprising two consecutive binary states. The first state is always different
from the second state of the previous symbol. The second state is identical to the first if the bit to be sent is Logic 0, but it
is different if the bit is Logic 1 (see
Source Coding
Channel Coding
(Biphase mark)
4.10.3.4 Keep-Alive Mode
The Keep-Alive Mode in the S/PDIF transmitter output is used to force a valid S/PDIF stream (clocking and status
information without data bits) to be output from the SPDIF_TX pin while the system is in a low power state. This allows an
external S/PDIF receiver to remain locked to the S/PDIF stream from the CS42L42 and resume playback without delay if
an output stream is later opened. The status information is provided according to the channel status bits in
The state of the SPDIF_TX pin depends on
shows all control-bit combinations and the resulting state of the SPDIF_TX pin. Note that
has no function in the Keep-Alive Mode on the CS42L42.
SPDIF_TX_DIGEN (see

4.11 Sample-Rate Converters (SRCs)

SRCs bridge different sample rates at the serial ports within the digital-processing core. SRCs are used for the following:
DS1083F2
Y Z
W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2 M
Subframe
Frame 191
Figure 4-39. S/PDIF Frame Format
3 4 7 8
L
Sync
Aux
Audio Sample Word
S
B
Figure 4-40. Subframe Format (Linear PCM Application)
Fig. 4-41).
Clock
Figure 4-41. S/PDIF Channel Coding
SPDIF_TX_DIGEN
Table 4-20. S/PDIF Output Keep-Alive Control
p. 161)
x
0
1
Y X
Subframe
Frame 0
Start of Block
Fig.
27 28
M
V U C P
S
B
Validity flag
User data
(see p. 162) and
SPDIF_TX_PDN (see p. 161)
1
0
0
4.11 Sample-Rate Converters (SRCs)
Y X
Frame 1
4-40.
31
Parity bit
Channel sta
SPDIF_TX_PDN (see p.
SPDIF_TX_KAE
SPDIF_TX
Off (drive low)
Clock + status
Clock + status + data
CS42L42
Table 4-20.
161). Table 4-20
(see p. 161)
75