Dac Control Registers - Cirrus Logic CS42L42 Manual

7.11.4 ADC Wind-Noise Filter and HPF
R/W
7
Default
0
Bits Name
7 — Reserved
6:4 ADC_ ADC wind-noise filter select. Sets the corner frequency for the wind-noise filter. See
WNF_CF
000–111 (Default = 111). See
3 ADC_ Enable ADC wind-noise filter. See
WNF_EN
0 (Default) Wind-noise filter disabled and bypassed.
1 Enabled
2:1 ADC_ HS ADC HPF corner frequency. Sets the corner frequency (–3 dB point) for the internal HPF. See
HPF_CF Increasing the HPF corner frequency past the default setting can introduce up to ~0.3 dB of gain error in the passband.
00 (Default) 3.88x10
01 2.5x10
0 ADC_ HS ADC HPF enable. Configures the internal HPF after the HS ADC. Change only if the ADC is in a powered down state.
HPF_EN See Section 4.1
of the ADC digital output.
0 Disabled. This must be cleared only for test purposes.
1 (Default) Enabled

7.12 DAC Control Registers

7.12.1 DAC Control 1
R/W
7
Default 0
Bits Name
7:2 — Reserved
1:0 DACx_INV DACx invert signal polarity. Configures the polarity of the DAC channel x signal. See
0 (Default) Not inverted
1 Inverted
7.12.2 DAC Control 2
R/W
7
Default 0
Bits Name
7:4 HPOUT_ Although bits 2:0 are independent, the final resistance from the resistor string is dictated by the lowest resistance chosen;
PULLDOWN e.g., if HPOUT_PULLDOWN = 1011, a nominal 6-k pull-down resistance results even if 9.6-k resistance is also
selected.
0000 (Default) 0.9 k
0001–0111 0.9 k
3 HPOUT_ HP output load. Sets HP amplifier capacitive load capability.
LOAD details.
0 (Default) 1 nF Mode
1 10 nF Mode
Note: The HP path must be powered down before reconfiguring this bit and repowered afterwards. See
2 HPOUT_ HPOUT clamp. Configures an override of the HPOUT clamp to ground when the channels are powered down.
CLAMP
0 (Default) Clamp to ground when channels are powered down.
1 Clamp is disabled when the channels are powered down. The pulldown to GNDA depends on the HPOUT_
PULLDOWN setting.
1 DAC_HPF_ DAC high-pass filter enable. Configures the internal HPF before DAC. Changes to this bit must be made only if PDN_
EN ALL = 1. See
0 Disabled. This must be cleared only for test purposes.
1 (Default) Enabled. The corner frequency is set to 0.935 Hz when
0 — Reserved
DS1083F2
6 5
ADC_WNF_CF
1 1
Table 3-11.
Section 4.1.2
–5 x (1.86 Hz at
Fs
INT
–3 x (120 Hz at = 48 kHz)
Fs Fs
INT INT
for details. ADC_HPF_EN must remain asserted for proper functionality. Failure to do so may cause clipping
6 5
—
0 0
6 5
HPOUT_PULLDOWN
0 0
1000 No pulldown
1001 9.3 k
Section 4.4 for details.
4 3
ADC_WNF_EN
1 0
Description
for details.
= 48 kHz) 10 4.9x10 –3
Fs
INT
11 9.7x10 –3
4 3
0 0
Description
4 3
HPOUT_LOAD HPOUT_CLAMP DAC_HPF_EN
0 0
Description
1010 5.8 k
1011 Reserved
Table 3-13 gives output specifications. See
Fs
INT
7.12 DAC Control Registers
2 1
ADC_HPF_CF
0 0
Section 4.1.2 for details.
Section 4.1
x (235 Hz at = 48 kHz)
Fs Fs
INT INT
x (466 Hz at = 48 kHz)
Fs Fs
INT INT
2 1
DACB_INV
0 0
Section 4.4 for details.
2 1
0 1
1100 0.9 k
1101–1111 Reserved
= 48 kHz.
CS42L42
Address 0x1D04
0
ADC_HPF_EN
1
for details.
Address 0x1F01
0
DACA_INV
0
Address 0x1F06
0
—
0
Section 4.4 for
Section 4.4.4.
154