Cirrus Logic CS42L42 Manual page 150

Bits Name
5 TIP_SENSE_ Tip sense invert. Used to invert the signal from the tip-sense circuit.
INV
0 (Default) Not inverted
1 Inverted
4:2 — Reserved
1:0 TIP_SENSE_ Tip sense debounce time. Sets tip sense unplug event (TIP_SENSE = 0) debounce time before status is reported.
DEBOUNCE Timings are approximate and vary with MCLK
00 No debounce
7.9.5 Miscellaneous Detect Control
R/W
7
Default
0
Bits Name
7:5 — Reserved
4:3 DETECT_ Detection mode setting.
MODE TO_VP (see
00 (Default) Inactive (SHORT_DETECTED and SHORT_RELEASE in the VP domain are also cleared)
01 Short detect only. Normal interrupts do not function; the INT pin follows the S0 comparator directly while the SHORT_
DETECTED mask is cleared and remains high while the SHORT_DETECTED mask is set.
10 Reserved
11 Normal Mode. HSBIAS output uses a high-performance reference for 2.0- or 2.7-V Mode. See HSBIAS_CTRL.
If LATCH_TO_VP = 1, PDN_ALL = 1 overrides DETECT_MODE setting and powers down the CS42L42.
2:1 HSBIAS_ HS bias output control.
CTRL
00 Output is Hi-Z. The HSBIAS output uses a low-performance, low-power reference. If the HSBIAS-to-HS4 switch is
closed (SW_HSB_HS4 = 1), the HS4 pin can float unless terminated with a load of at least 100 k
01 (Default) 0.0 V (weak ground, see
10 2.0 V. Wait for circuits to completely power up. A setting of 10 or 11 is required for headset interface functionality.
11 2.7 V. Wait for circuits to completely power up. A setting of 10 or 11 is required for headset interface functionality.
Note: If DETECT_MODE = 11, the HSBIAS output uses a high-performance reference. If DETECT_MODE  11, the
HSBIAS output uses a low-performance, low-power reference.
• To avoid audible artifacts if the HS path is active, the path must be muted before changing the HSBIAS settings.
• LATCH_TO_VP = 1, PDN_ALL = 1 overrides HSBIAS_CTRL settings and powers down the CS42L42.
• Table 3-15
for the effect of DETECT_MODE. It also documents HS bias power-up time.
0 PDN_MIC_ Power-down mic DC level detect. Configures the power state of the mic-level detect circuit.
LVL_
0 Powered up. See
DETECT
1 (Default) Powered down
This feature can be used at any time (set in parallel with any other detection mode), but should not be continuously enabled
if the HS input is enabled because the HS noise performance is degraded.
1.This bit can be updated only if
7.9.6 Mic Detect Control 1
R/W
7
LATCH_TO_VP EVENT_STATUS_SEL
Default
0
Bits Name
7 LATCH_ Latch to VP registers. Controls the transfer of writable control registers in the VD_FILT supply domain to duplicate registers
TO_VP in the VP supply domain. Can be used to enable setting sticky status bits in the VP domain.
0 (Default) Inhibits the transfer of VD_FILT registers to VP registers (latched mode). Enables the setting of VP sticky
status latches.
1 Transfers VD_FILT fields to VP fields (transparent mode). Disables setting of VP sticky status latches.
Affected registers:
• DETECT_MODE on p. 150
• TIP_SENSE_EN on p. 149
• M_MIC_WAKE on p. 149
Note: The description of
DS1083F2
01 200 ms
6 5
—
0 0
1 Sets the appropriate mode to be used for the mic button detection. This bit is affected by
p. 150).
1 Sets the mode for the HSBIAS output pin. See the DETECT_MODE description, above.
Table
more precisely specifies voltages present on the HSBIAS output for each HSBIAS_CTRL setting, accounting
Table 3-14 for the level detect power-up time.
LATCH_TO_VP is enabled.
6 5
0 0
•
•
• HSBIAS_CTRL on p. 150
•
•
PDN_ALL on p. 131
Description
Updatable only if
and Fs .
INT INT
10 (Default) 500 ms
4 3
DETECT_MODE
0 0
Description
3-14, Footnote 1).
4 3
HS_DETECT_LEVEL
1 1
Description
M_HP_WAKE on p. 149
M_SHORT_DETECTED on p. 152
SW_REF_HSx on p. 135
SW_HSB_FILT_HSx on p. 135
describes the interdependency between LATCH_TO_VP and PDN_ALL.
7.9 Headset Interface Registers
LATCH_TO_VP is enabled.
11 1000 ms
2 1
HSBIAS_CTRL
0 1
2 1
1 1
• SW_HSB_HSx on p. 135
• SW_GNDHS_HSx on p. 135
• WAKEB_MODE p. 149
CS42L42
Address 0x1B74
0
PDN_MIC_LVL_
DETECT
1
LATCH_
Address 0x1B75
0
1
150