Serial Port Register Transmit Registers - Cirrus Logic CS42L42 Manual

Bits Name
1 SPDIF_ Validity. Affects the validity flag (V) bit 28, transmitted in each subframe in conjunction with the SPDIF_TX_VCFG setting.
TX_V
0 (default) enables the S/PDIF transmitter to maintain connection during error or mute conditions.
1 The V bit in the subframe is always set to indicate invalid data
SPDIF_ SPDIF_
TX_VCFG
0
1
0
1
0 SPDIF_ S/PDIF transmit enable. Determines whether data can be driven onto the S/PDIF output.
TX_
0 (Default) Data cannot be driven onto the S/PDIF output. See
DIGEN
1 Data can be driven onto the S/PDIF output. See
7.20.3 S/PDIF Control 3
R/W
7
—
Default 0
Bits Name
7 — Reserved
6:0 SPDIF_TX_ S/PDIF transmit category code. Program according to the IEC60958-3 specification.
CC
000 0000 (Default)
7.20.4 S/PDIF Control 4
R/W
7
Default
0
Bits Name
7:3 — Reserved
2:0 SPDIF_TX_ S/PDIF transmit state. Configures the supported S/PDIF rate. See
STAT 000 32 kHz
001 44.1 kHz

7.21 Serial Port Register Transmit Registers

7.21.1 ASP Transmit Size and Enable
R/W
7
Default 0
Bits Name
7:2 — Reserved
1 ASP_ ASP channel data requests per frame. Used to configure the TX into Fs or 2Fs Mode.
TX_
0 (Default) Fs Mode
2FS
1 2Fs Mode (doubles the incoming LRCK rate)
0 ASP_ ASP TDM TX channel output enable. Configures the electrical state of the channel output phase determined by ASP_TX_CHx_RES.
TX_
0 (Default) Not enabled (Hi-Z)
EN
1 Enabled (driven)
DS1083F2
TX_V
0 (Default) For each S/PDIF subframe (left and right), the validity flag reflects whether an internal codec
error occurred (i.e., whether the S/PDIF interface received and transmitted a valid sample).
If a valid sample (left or right) is received and successfully transmitted, the V bit is cleared for that
subframe. Otherwise, the V bit for that subframe must be transmitted as 1.
0 For each S/PDIF subframe (left and right), the V bit reflects whether an internal codec transmission
error occurred (i.e., an internal codec error should set the V bit).
• If a valid sample (left or right) is received and successfully transmitted, the V bit is cleared for that
subframe.
• If the S/PDIF transmitter is not receiving a sample, the S/PDIF transmitter must set the V bit and pad
each S/PDIF audio sample word in question with zeros for the corresponding subframe.
1 Each S/PDIF subframe (left and right) is sent with the V bit set. This tags all S/PDIF subframes as
invalid.
1 Reserved
6 5
0 0
6 5
—
1 0
010 (Default) 48 kHz
011 88.2 kHz
6 5
—
0 0
7.21 Serial Port Register Transmit Registers
Description
Description
Table 4-20.
Table 4-20.
4 3
SPDIF_TX_CC
0 0
Description
4 3
0 0
Description
Section 4.10.1
100 96 kHz
101 176.4 kHz
4 3
0 0
Description
CS42L42
Address 0x2803
2 1
0 0
Address 0x2804
2 1
SPDIF_TX_STAT
0 1
for details.
110 192 kHz
111 Reserved
Address 0x2901
2 1
ASP_TX_2FS ASP_TX_EN
0 0
0
0
0
0
0
0
162