Cirrus Logic CS42L42 Manual page 83

Table 4-27. Typical Leakage Current during Nonoperational Supply States (with VP Powered On)
Supply
VCP VA
Off On
Off On
On Off
On Off
On On
On On
Notes: • Values shown reflect typical voltage and temperature. Leakage current may vary by orders of magnitude across the maximum
and minimum recommended operating supply voltages and temperatures listed in
• Test conditions: Clock/data lines are held low, RESET is held high, and all registers are set to their default values.
Table 4-28 shows requirements and available features for valid power-supply configurations.
Configuration
On: VP
Off: VD_FILT = VCP = VL = VA
On: VP = VL
Off: VD_FILT = VCP = VA = OFF
On: VP = VD_FILT = VCP = VL = VA
4.15.1 VP Monitor
The CS42L42 voltage comparator monitors the VP power supply for potential brown-out conditions due to power-supply
overload or other fault conditions. To perform according to specifications, VP is expected to remain above 3.0 V at all
times. The VP monitor is enabled by setting
The following describes the VP monitor behavior with respect to the voltage level:
• If VP drops below 3.0 V, HSBIAS, HP output, RING_SENSE, and TIP_SENSE performance may be compromised.
• If VP drops below 2.6 V, the
TRIP = 0 (see p. 146). This bit must be unmasked/enabled only if VP is above the detection-voltage threshold. It
must be masked/disabled by default to eliminate erroneous interrupts while VP is ramping or is known to be below
the threshold voltage.
• A brown-out condition remains until VP returns to a voltage level above 3.0 V.
• The VP monitor circuit becomes unreliable at VP levels below 2.4 V.
• The VP monitor is intended to detect slow transitioning signals about the 2.6-V threshold. Pulses of short duration
are filtered by the monitor and may not trigger at the 2.6-V threshold, but at a value much lower than expected.
DS1083F2
VL I
Vp
Off 14
On 25
Off 14
On 25
Off 14
On 25
Table 4-28. Valid Power-Supply Configurations
Limited set of headset plug-detect and WAKE output features, see
Limited set of headset plug-detect and WAKE output features, see
Digital I/O ESD diodes are powered to prevent conduction in pin-sharing applications.
Full chip functionality
VPMON_PDNB
3.6 V
3.0 V
2.6 V
VPMON_TRIP
Figure 4-46. VP Monitor
VPMON_TRIP status bit is set (see
Current (µA)
I I
VCP VA
0 0
0 0
0 0
0 0
0 0
0 0
Notes
(see p. 132). Fig. 4-46
p. 143). An interrupt is triggered if
4.15 Power-Supply Considerations
Notes
I
VL
0 VA may source or sink current
328 VA may source or sink current
0 —
328 —
0 VA may source or sink current
328 —
Table 3-2.
Section 4.12 and
Section 4.12 and
shows the behavior of the VP monitor.
CS42L42
Section 4.13.
Section 4.13.
M_VPMON_
83