Cirrus Logic CS42L42 Manual page 24

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Table 3-20. S0 Button Detect Characteristics
Test conditions (unless specified otherwise):
parameters can vary with VA and VP; typical performance data taken with VL = VA = 1.8 V, VP = 3.6 V; min/max performance data taken with
VA = 1.66–1.94 V, VL = 1.8 V, VP = 3.0–5.25 V; T
HS DC-detection Short-detect threshold (S0 button)
parameters
Total group delay
HS DC detect threshold
DC level detect power-up time
1.The variable M refers to the decimal representation of the
2.Time for the DC level detector circuits to completely power up after
Table 3-21. Switching Specifications—SoundWire Port
Test conditions (unless specified otherwise): GND = 0 V; SWIRE_SEL pin = VL; voltages are with respect to ground; VD_FILT = 1.2 V; VA = 1.8 V;
VP = 3.6 V; TA = +25°C; logic 0 = ground, logic 1 = VL; input timings are measured at V
V thresholds for VL logic (as shown in
OH
VL = 1.2 SWIRE_CLK frequency
Input clock slew time
Data output slew time
Data driver disable time
Delay from clock to active state
Time for data output valid
Data output hold time
Data input minimum setup time
Data input minimum hold time
Clock input duty cycle
VL logic (SWIRE_CLK and
SWIRE_SD pins)
DS1083F2
Table 3-19. Register Field Settings
Register Fields and Settings
Use
Cases
1 A — — — — — — — — — — — 00 00 01 —
A 1 — — — — — — — 1 0 — 01 01 10 0
2
B 1 — — — — — — — 1 0 — 01 01 10 1
3 A 1 — — — — — — — 1 0 — 01 01 10 0
B 1 — — — — — — — 1 0 — 01 01 10 1
4 A 0 0 1 1 0 1 1 1 1 0 0 00 00 00 0
5 A 0 1 0 1 1 0 1 0 1 0 0 01 00 10 1
B 0 1 0 1 1 0 1 0 1 0 0 01 00 10 1
6 A 0 1 0 1 1 1 1 1 0 0 0 00 00 00 1
7 A Individual power downs.
See definitions in
1.LATCH_TO_VP must be set for the following settings to take effect: TIP_
SENSE_CTRL, DETECT_MODE, HS_CLAMP_DISABLE, HSBIAS_CTRL.
Fig. 2-1 shows CS42L42 connections; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground;
= +25°C.
A
Parameters
1
2
HS_DETECT_LEVEL
Table 3-25).
Parameter
Small data bus (
Large data bus (
1
2
Small data bus (
Large data bus (
2
Input voltage threshold (rising edge)
Input voltage threshold (falling edge)
Class H Mode
Table 3-18.
setting (see p. 151).
PDN_MIC_LVL_DETECT transitions from 1 to 0 (see
and V thresholds; output timings are measured at V
IL IH
10- to 60-pF capacitance)
10- to 100-pF capacitance)
Small data bus
Large data bus
10- to 60-pF capacitance)
10- to 100-pF capacitance)
T
ISETUP_MIN_DATA
T
IHOLD_MIN_DATA
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
Hysteresis voltage
3 Characteristics and Specifications
p. 41
—
—
—
—
—
—
VCP/3
VCP/3
—
—
Minimum Typical
100 150
— 5
— (M+1) x 1.5625
— 11
p. 150).
Symbol Minimum Maximum
F —
SWSCLK
—
— 2.0
— 2.0
T 2.0
SLEW
T —
DZ
T 8.1
ZD
T —
OV_DATA
—
T 6.7
OH_DATA
—
—
— 45
V 0.8*VL
OH
V —
OL
V 0.65*VL
IH
V —
IL
V 0.5*VL
TP
V 0.35*VL
TN
V 0.1*VL
HYST
CS42L42
Maximum Unit
200 mV
— ms
— %
— ms
and
OL
Unit
12.3 MHz
11.0 MHz
5.0 ns
6.0 ns
— ns
5.0 ns
— ns
27.9 ns
29.0 ns
— ns
0.0 ns
4.0 ns
55 %
— V
0.2*VL V
— V
0.35*VL V
0.65*VL V
0.5*VL V
— V
24