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User Manuals: Cirrus Logic CS4265 Amplifier System
Manuals and User Guides for Cirrus Logic CS4265 Amplifier System. We have
1
Cirrus Logic CS4265 Amplifier System manual available for free PDF download: Manual
Cirrus Logic CS4265 Manual (57 pages)
104 dB, 24-Bit, 192 kHz Stereo Audio CODEC
Brand:
Cirrus Logic
| Category:
Conference System
| Size: 1 MB
Table of Contents
Table of Contents
3
1 Pin Descriptions
7
2 Characteristics and Specifications
9
Specified Operating Conditions
9
Absolute Maximum Ratings
9
Dac Analog Characteristics
10
Dac Combined Interpolation & On-Chip Analog Filter Response
11
Figure 1.DAC Output Test Load
12
Figure 2.Maximum DAC Loading
12
Adc Analog Characteristics
13
Adc Analog Characteristics
15
Adc Digital Filter Characteristics
16
DC Electrical Characteristics
17
Digital Interface Characteristics
18
Switching Characteristics - Serial Audio Port
19
Figure 3.Master Mode Serial Audio Port Timing
20
Figure 4.Slave Mode Serial Audio Port Timing
20
Figure 5.Format 0, Left-Justified up to 24-Bit Data
21
Figure 6.Format 1, I²S up to 24-Bit Data
21
Figure 7.Format 2, Right-Justified 16-Bit Data
21
Format 3, Right-Justified 24-Bit Data
21
Switching Characteristics - I²C Control Port
22
Figure 8.Control Port Timing - I²C Format
22
3 Typical Connection Diagram
23
Figure 9.Typical Connection Diagram
23
4 Applications
24
Recommended Power-Up Sequence
24
System Clocking
24
Master Clock
24
Table 1. Speed Modes
24
Table 2. Common Clock Frequencies
24
Master Mode
25
Slave Mode
25
High-Pass Filter and DC Offset Calibration
25
Figure 10.Master Mode Clocking
25
Table 3. MCLK Dividers
25
Table 4. Slave Mode Serial Bit Clock Ratios
25
Analog Input Multiplexer, PGA, and MIC Gain
27
Input Connections
27
Pseudo-Differential Input
27
Figure 11.Analog Input Architecture
27
Output Connections
28
Output Transient Control
28
Power-Up
28
Power-Down
28
Serial Interface Clock Changes
28
Figure 12.Pseudo-Differential Input Stage
28
DAC Serial Data Input Multiplexer
29
De-Emphasis Filter
29
Internal Digital Loopback
29
Figure 13.De-Emphasis Curve
29
Mute Control
30
AES3 Transmitter
30
Txout Driver
30
Figure 14.Suggested Active-Low Mute Circuit
30
Mono Mode Operation
31
I²C Control Port Description and Timing
31
Status Reporting
32
Figure 15.Control Port Timing, I²C Write
32
Figure 16.Control Port Timing, I²C Read
32
Reset
33
Synchronization of Multiple Devices
33
Grounding and Power Supply Decoupling
33
Package Considerations
33
5 Register Quick Reference
34
6 Register Description
36
Chip ID - Register 01H
36
Power Control - Address 02H
36
Freeze (Bit 7)
36
Power-Down MIC (Bit 3)
36
Power-Down ADC (Bit 2)
36
Table 5. Device Revision
36
Table 6. Freeze-Able Bits
36
Power-Down DAC (Bit 1)
37
Power-Down Device (Bit 0)
37
DAC Control - Address 03H
37
DAC Digital Interface Format (Bits 5:4)
37
Mute DAC (Bit 2)
37
Table 7. DAC Digital Interface Formats
37
De-Emphasis Control (Bit 1)
38
ADC Control - Address 04H
38
Functional Mode (Bits 7:6)
38
ADC Digital Interface Format (Bit 4)
38
Figure 17.De-Emphasis Curve
38
Table 8. De-Emphasis Control
38
Table 9. Functional Mode Selection
38
Mute ADC (Bit 2)
39
ADC High-Pass Filter Freeze (Bit 1)
39
Master / Slave Mode (Bit 0)
39
MCLK Frequency - Address 05H
39
Master Clock Dividers (Bits 6:4)
39
Table 10. ADC Digital Interface Formats
39
Table 11. MCLK Frequency
39
Signal Selection - Address 06H
40
DAC SDIN Source (Bit 7)
40
Digital Loopback (Bit 1)
40
Channel B PGA Control - Address 07H
40
Channel B PGA Gain (Bits 5:0)
40
Channel a PGA Control - Address 08H
40
Channel a PGA Gain (Bits 5:0)
40
Table 12. DAC SDIN Source Selection
40
Table 13. Example Gain and Attenuation Settings
40
ADC Input Control - Address 09H
41
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
41
Analog Input Selection (Bit 0)
41
DAC Channel a Volume Control - Address 0Ah
41
Table 14. PGA Soft Cross or Zero Cross Mode Selection
41
Table 15. Analog Input Selection
41
DAC Channel B Volume Control - Address 0Bh
42
Volume Control (Bits 7:0)
42
DAC Control 2 - Address 0Ch
42
DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
42
Table 16. Digital Volume Control Example Settings
42
Invert DAC Output (Bit 5)
43
Status - Address 0Dh
43
E to F C-Buffer Transfer
43
Clock Error (Bit 3)
43
ADC Overflow (Bit 1)
43
ADC Underflow (Bit 0)
43
Table 17. DAC Soft Cross or Zero Cross Mode Selection
43
Status Mask - Address 0Eh
44
Status Mode MSB - Address 0Fh
44
Status Mode LSB - Address 10H
44
Transmitter Control 1 - Address 11H
44
E to F C-Data Buffer Transfer Inhibit (Bit 6)
44
C-Data Access Mode (Bit 5)
44
Transmitter Control 2 - Address 12H
45
Transmitter Digital Interface Format (Bits 7:6)
45
Transmitter Output Driver Control (Bit 5)
45
Transmitter Mute Control (Bit 4)
45
Transmitted Validity Bit Control (Bit 3)
45
Transmitter Mono/Stereo Operation Control (Bit 2)
45
Mono Mode CS Data Source (Bit 1)
45
Table 18. Transmitter Digital Interface Formats
45
Mono Mode Channel Selection (Bit 0)
46
7 Parameter Definitions
47
8 Dac Filter Plots
48
Figure 18.DAC Single-Speed Stopband Rejection
48
Figure 19.DAC Single-Speed Transition Band
48
Figure 20.DAC Single-Speed Transition Band
48
Figure 21.DAC Single-Speed Passband Ripple
48
Figure 22.DAC Double-Speed Stopband Rejection
48
Figure 23.DAC Double-Speed Transition Band
48
Figure 24.DAC Double-Speed Transition Band
49
Figure 25.DAC Double-Speed Passband Ripple
49
Figure 26.DAC Quad-Speed Stopband Rejection
49
Figure 27.DAC Quad-Speed Transition Band
49
Figure 28.DAC Quad-Speed Transition Band
49
Figure 29.DAC Quad-Speed Passband Ripple
49
9 Adc Filter Plots
50
Figure 30.ADC Single-Speed Stopband Rejection
50
Figure 31.ADC Single-Speed Stopband Rejection
50
Figure 32.ADC Single-Speed Transition Band (Detail)
50
Figure 33.ADC Single-Speed Passband Ripple
50
Figure 34.ADC Double-Speed Stopband Rejection
50
Figure 35.ADC Double-Speed Stopband Rejection
50
Figure 36.ADC Double-Speed Transition Band (Detail)
51
Figure 37.ADC Double-Speed Passband Ripple
51
Figure 38.ADC Quad-Speed Stopband Rejection
51
Figure 39.ADC Quad-Speed Stopband Rejection
51
Figure 40.ADC Quad-Speed Transition Band (Detail)
51
Figure 41.ADC Quad-Speed Passband Ripple
51
10 External Iec60958-3 Transmitter Components
52
IEC60958-3 Transmitter External Components
52
Isolating Transformer Requirements
52
Figure 42.Consumer Output Circuit (VD = 5 V)
52
Figure 43.TTL/CMOS Output Circuit
52
11 Channel Status Buffer Management
53
IEC60958-3 Channel Status (C) Bit Management
53
Figure 44.Channel Status Data Buffer Structure
53
Accessing the E Buffer
54
Serial Copy Management System (SCMS)
54
Channel Status Data E Buffer Access
54
Figure 45.Flowchart for Writing the E Buffer
54
One-Byte Mode
55
Two-Byte Mode
55
12 Package Dimensions
56
13 Thermal Characteristics and Specifications
56
14 Ordering Information
57
15 Revision History
57
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